| Line 40... |
Line 40... |
-- Signals used to control the configuration
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-- Signals used to control the configuration
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signal startConfigBaud : std_logic;
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signal startConfigBaud : std_logic;
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signal startConfigClk : std_logic;
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signal startConfigClk : std_logic;
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signal startDataSend : std_logic;
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signal startDataSend : std_logic;
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signal commBlocksInitiated : std_logic;
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signal commBlocksInitiated : std_logic;
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signal doneWriteReg : std_logic;
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signal startReadReg : std_logic;
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signal startReadReg : std_logic;
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signal alreadyConfBaud : std_logic;
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signal alreadyConfBaud : std_logic;
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signal alreadyConfClk : std_logic;
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signal alreadyConfClk : std_logic;
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-- Divisor component
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-- Divisor component
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| Line 80... |
Line 79... |
config_baud <= (others => '0');
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config_baud <= (others => '0');
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byte_to_transmit <= (others => '0');
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byte_to_transmit <= (others => '0');
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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startDataSend <= '0';
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startDataSend <= '0';
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doneWriteReg <= '0';
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alreadyConfClk <= '0';
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alreadyConfClk <= '0';
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alreadyConfBaud <= '0';
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alreadyConfBaud <= '0';
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elsif (WE and start) = '1' then
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elsif (WE and start) = '1' then
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case reg_addr is
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case reg_addr is
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when "00" =>
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when "00" =>
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| Line 98... |
Line 96... |
startConfigBaud <= '1';
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startConfigBaud <= '1';
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startDataSend <= '0';
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startDataSend <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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alreadyConfBaud <= '1';
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alreadyConfBaud <= '1';
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when "10" =>
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when "10" =>
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-- If we have an overrun, discard the byte
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byte_to_transmit <= DAT_I((nBits-1) downto 0);
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byte_to_transmit <= DAT_I((nBits-1) downto 0);
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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startDataSend <= '1';
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startDataSend <= '1';
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when others =>
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when others =>
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startConfigBaud <= '0';
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startConfigBaud <= '0';
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startConfigClk <= '0';
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startConfigClk <= '0';
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startDataSend <= '0';
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startDataSend <= '0';
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end case;
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end case;
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else
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startDataSend <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process to handle the reading of registers
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-- Process to handle the reading of registers
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| Line 150... |
Line 149... |
end if;
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end if;
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end process;
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end process;
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-- Process to send data over the serial transmitter
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-- Process to send data over the serial transmitter
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process (clk)
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process (clk)
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variable cont_steps : integer range 0 to 3;
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variable sendDataStates : sendByte;
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if (rst = '1') then
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if (rst = '1') then
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cont_steps := 0;
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sendDataStates := idle;
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else
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else
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case sendDataStates is
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when idle =>
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if commBlocksInitiated = '1' and startDataSend = '1' then
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if commBlocksInitiated = '1' and startDataSend = '1' then
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case cont_steps is
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sendDataStates := prepare_byte;
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when 0 =>
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end if;
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when prepare_byte =>
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data_byte_tx <= byte_to_transmit;
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data_byte_tx <= byte_to_transmit;
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tx_start <= '0';
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tx_start <= '0';
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when 1 =>
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sendDataStates := start_sending;
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when start_sending =>
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tx_start <= '1';
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tx_start <= '1';
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when others =>
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sendDataStates := wait_completion;
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null;
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end case;
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when wait_completion =>
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if cont_steps < 3 then
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if tx_data_sent = '1' then
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cont_steps := cont_steps + 1;
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sendDataStates := idle;
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else
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cont_steps := 3;
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end if;
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end if;
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end if;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
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-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
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| Line 213... |
Line 216... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
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-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
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process (startConfigBaud,startConfigClk, clk)
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process (alreadyConfClk,alreadyConfBaud, clk)
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variable cont_steps : integer range 0 to 3;
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variable cont_steps : integer range 0 to 3;
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begin
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begin
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if (alreadyConfClk and alreadyConfBaud) = '0' then
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if (alreadyConfClk and alreadyConfBaud) = '0' then
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sigDivRst <= '1';
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sigDivRst <= '1';
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cont_steps := 0;
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cont_steps := 0;
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