Line 40... |
Line 40... |
-- Signals used to control the configuration
|
-- Signals used to control the configuration
|
signal startConfigBaud : std_logic;
|
signal startConfigBaud : std_logic;
|
signal startConfigClk : std_logic;
|
signal startConfigClk : std_logic;
|
signal startDataSend : std_logic;
|
signal startDataSend : std_logic;
|
signal commBlocksInitiated : std_logic;
|
signal commBlocksInitiated : std_logic;
|
signal doneWriteReg : std_logic;
|
|
signal startReadReg : std_logic;
|
signal startReadReg : std_logic;
|
signal alreadyConfBaud : std_logic;
|
signal alreadyConfBaud : std_logic;
|
signal alreadyConfClk : std_logic;
|
signal alreadyConfClk : std_logic;
|
|
|
-- Divisor component
|
-- Divisor component
|
Line 80... |
Line 79... |
config_baud <= (others => '0');
|
config_baud <= (others => '0');
|
byte_to_transmit <= (others => '0');
|
byte_to_transmit <= (others => '0');
|
startConfigBaud <= '0';
|
startConfigBaud <= '0';
|
startConfigClk <= '0';
|
startConfigClk <= '0';
|
startDataSend <= '0';
|
startDataSend <= '0';
|
doneWriteReg <= '0';
|
|
alreadyConfClk <= '0';
|
alreadyConfClk <= '0';
|
alreadyConfBaud <= '0';
|
alreadyConfBaud <= '0';
|
elsif (WE and start) = '1' then
|
elsif (WE and start) = '1' then
|
case reg_addr is
|
case reg_addr is
|
when "00" =>
|
when "00" =>
|
Line 98... |
Line 96... |
startConfigBaud <= '1';
|
startConfigBaud <= '1';
|
startDataSend <= '0';
|
startDataSend <= '0';
|
startConfigClk <= '0';
|
startConfigClk <= '0';
|
alreadyConfBaud <= '1';
|
alreadyConfBaud <= '1';
|
when "10" =>
|
when "10" =>
|
-- If we have an overrun, discard the byte
|
|
byte_to_transmit <= DAT_I((nBits-1) downto 0);
|
byte_to_transmit <= DAT_I((nBits-1) downto 0);
|
startConfigBaud <= '0';
|
startConfigBaud <= '0';
|
startConfigClk <= '0';
|
startConfigClk <= '0';
|
startDataSend <= '1';
|
startDataSend <= '1';
|
when others =>
|
when others =>
|
startConfigBaud <= '0';
|
startConfigBaud <= '0';
|
startConfigClk <= '0';
|
startConfigClk <= '0';
|
startDataSend <= '0';
|
startDataSend <= '0';
|
end case;
|
end case;
|
|
else
|
|
startDataSend <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Process to handle the reading of registers
|
-- Process to handle the reading of registers
|
Line 150... |
Line 149... |
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Process to send data over the serial transmitter
|
-- Process to send data over the serial transmitter
|
process (clk)
|
process (clk)
|
variable cont_steps : integer range 0 to 3;
|
variable sendDataStates : sendByte;
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if (rst = '1') then
|
if (rst = '1') then
|
cont_steps := 0;
|
sendDataStates := idle;
|
else
|
else
|
|
case sendDataStates is
|
|
when idle =>
|
if commBlocksInitiated = '1' and startDataSend = '1' then
|
if commBlocksInitiated = '1' and startDataSend = '1' then
|
case cont_steps is
|
sendDataStates := prepare_byte;
|
when 0 =>
|
end if;
|
|
|
|
when prepare_byte =>
|
data_byte_tx <= byte_to_transmit;
|
data_byte_tx <= byte_to_transmit;
|
tx_start <= '0';
|
tx_start <= '0';
|
when 1 =>
|
sendDataStates := start_sending;
|
|
|
|
when start_sending =>
|
tx_start <= '1';
|
tx_start <= '1';
|
when others =>
|
sendDataStates := wait_completion;
|
null;
|
|
end case;
|
when wait_completion =>
|
if cont_steps < 3 then
|
if tx_data_sent = '1' then
|
cont_steps := cont_steps + 1;
|
sendDataStates := idle;
|
else
|
|
cont_steps := 3;
|
|
end if;
|
|
end if;
|
end if;
|
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
|
-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
|
Line 213... |
Line 216... |
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
|
-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
|
process (startConfigBaud,startConfigClk, clk)
|
process (alreadyConfClk,alreadyConfBaud, clk)
|
variable cont_steps : integer range 0 to 3;
|
variable cont_steps : integer range 0 to 3;
|
begin
|
begin
|
if (alreadyConfClk and alreadyConfBaud) = '0' then
|
if (alreadyConfClk and alreadyConfBaud) = '0' then
|
sigDivRst <= '1';
|
sigDivRst <= '1';
|
cont_steps := 0;
|
cont_steps := 0;
|