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--! uart control unit
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--! @file
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--! @brief Uart control unit
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity uart_control is
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entity uart_control is
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Port ( rst : in std_logic; -- Global reset
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Port ( rst : in std_logic; --! Global reset
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clk : in std_logic; -- Global clock
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clk : in std_logic; --! Global clock
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WE : in std_logic; -- Write enable
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WE : in std_logic; --! Write enable
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reg_addr : in std_logic_vector (1 downto 0); -- Register address
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reg_addr : in std_logic_vector (1 downto 0); --! Register address
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start : in std_logic; -- Start (Strobe)
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start : in std_logic; --! Start (Strobe)
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done : out std_logic; -- Done (ACK)
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done : out std_logic; --! Done (ACK)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); --! Data Input (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); --! Data output (Wishbone)
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); --! Signal to control the baud rate frequency
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); --! 1 Byte to be send to serial_transmitter
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); --! 1 Byte to be received by serial_receiver
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_data_sent : in std_logic; --! Signal comming from serial_transmitter
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tx_start : out std_logic; -- Signal to start sending serial data...
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tx_start : out std_logic; --! Signal to start sending serial data...
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rst_comm_blocks : out std_logic; --! Reset Communication blocks
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rx_data_ready : in std_logic); -- Signal comming from serial_receiver
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rx_data_ready : in std_logic); --! Signal comming from serial_receiver
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end uart_control;
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end uart_control;
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--! @brief Uart control unit
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--! @details Configure, commands, the uart_communication_blocks
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architecture Behavioral of uart_control is
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architecture Behavioral of uart_control is
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal received_byte : std_logic_vector((nBits-1) downto 0);
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signal received_byte : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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done : out STD_LOGIC);
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done : out STD_LOGIC);
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end component;
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end component;
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begin
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begin
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-- Instantiate block for calculate division
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--! Instantiate block for calculate division
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uDiv : divisor port map (
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uDiv : divisor port map (
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rst => sigDivRst,
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rst => sigDivRst,
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clk => clk,
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clk => clk,
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quotient => sigDivQuotient,
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quotient => sigDivQuotient,
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reminder => open, -- Indicates that this port will not be connected to anything
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reminder => open, -- Indicates that this port will not be connected to anything
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