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--! Top wishbone slave for the uart
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--! @file
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--! @brief Top wishbone slave for the uart (Connects uart_control and uart_communication_blocks)
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity uart_wishbone_slave is
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entity uart_wishbone_slave is
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Port ( RST_I : in STD_LOGIC;
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Port ( RST_I : in STD_LOGIC; --! Reset Input
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CLK_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC; --! Clock Input
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ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0);
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ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0); --! Address input
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DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0);
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DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0); --! Data Input 0
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0);
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0); --! Data Output 0
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WE_I : in STD_LOGIC;
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WE_I : in STD_LOGIC; --! Write enable input
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STB_I : in STD_LOGIC;
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STB_I : in STD_LOGIC; --! Strobe input (Works like a chip select)
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ACK_O : out STD_LOGIC;
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ACK_O : out STD_LOGIC; --! Ack output
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serial_in : in std_logic;
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data_Avaible : out std_logic; -- Indicate that the receiver module got something
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-- NON-WISHBONE Signals
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serial_in : in std_logic; --! Uart serial input
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data_Avaible : out std_logic; --! Flag to indicate data avaible
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serial_out : out std_logic
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serial_out : out std_logic
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);
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);
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end uart_wishbone_slave;
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end uart_wishbone_slave;
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--! @brief Top uart_wishbone_slave architecture
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--! @details Connect the control unit and the communication blocks
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architecture Behavioral of uart_wishbone_slave is
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architecture Behavioral of uart_wishbone_slave is
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component uart_control is
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component uart_control is
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Port ( rst : in std_logic; -- Global reset
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Port ( rst : in std_logic; --! Global reset
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clk : in std_logic; -- Global clock
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clk : in std_logic; --! Global clock
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WE : in std_logic; -- Write enable
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WE : in std_logic; --! Write enable
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reg_addr : in std_logic_vector (1 downto 0); -- Register address
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reg_addr : in std_logic_vector (1 downto 0); --! Register address
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start : in std_logic; -- Start (Strobe)
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start : in std_logic; --! Start (Strobe)
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done : out std_logic; -- Done (ACK)
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done : out std_logic; --! Done (ACK)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); --! Data Input (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); --! Data output (Wishbone)
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); --! Signal to control the baud rate frequency
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); --! 1 Byte to be send to serial_transmitter
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); --! 1 Byte to be received by serial_receiver
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_data_sent : in std_logic; --! Signal comming from serial_transmitter
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tx_start : out std_logic; -- Signal to start sending serial data...
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tx_start : out std_logic; --! Signal to start sending serial data...
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rst_comm_blocks : out std_logic; --! Reset Communication blocks
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rx_data_ready : in std_logic);
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rx_data_ready : in std_logic);
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end component;
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end component;
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component uart_communication_blocks is
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component uart_communication_blocks is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Global reset
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; --! Global clock
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0); --! Number of cycles to wait in order to generate desired baud
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to transmit
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to receive
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data_sent_tx : out STD_LOGIC;
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data_sent_tx : out STD_LOGIC; --! Indicate that byte has been sent
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data_received_rx : out STD_LOGIC;
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data_received_rx : out STD_LOGIC; --! Indicate that we got a byte
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serial_out : out std_logic;
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serial_out : out std_logic; --! Uart serial out
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serial_in : in std_logic;
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serial_in : in std_logic; --! Uart serial in
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start_tx : in STD_LOGIC);
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start_tx : in STD_LOGIC); --! Initiate transmission
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end component;
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end component;
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signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
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signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
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signal tx_data_sent : std_logic;
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signal tx_data_sent : std_logic;
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signal tx_start : std_logic;
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signal tx_start : std_logic;
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signal rst_comm_blocks : std_logic;
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signal rst_comm_blocks : std_logic;
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signal rx_data_ready : std_logic;
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signal rx_data_ready : std_logic;
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signal data_byte_tx : std_logic_vector(7 downto 0);
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signal data_byte_tx : std_logic_vector(7 downto 0);
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signal data_byte_rx : std_logic_vector(7 downto 0);
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signal data_byte_rx : std_logic_vector(7 downto 0);
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begin
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begin
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-- Instantiate uart_control
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--! Instantiate uart_control
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uUartControl : uart_control port map (
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uUartControl : uart_control port map (
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rst => RST_I,
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rst => RST_I,
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clk => CLK_I,
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clk => CLK_I,
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WE => WE_I,
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WE => WE_I,
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reg_addr => ADR_I0,
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reg_addr => ADR_I0,
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rst_comm_blocks => rst_comm_blocks,
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rst_comm_blocks => rst_comm_blocks,
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tx_start => tx_start,
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tx_start => tx_start,
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rx_data_ready => rx_data_ready
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rx_data_ready => rx_data_ready
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);
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);
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-- Instantiate uart_communication_blocks
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--! Instantiate uart_communication_blocks
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uUartCommunicationBlocks : uart_communication_blocks port map (
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uUartCommunicationBlocks : uart_communication_blocks port map (
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rst => rst_comm_blocks,
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rst => rst_comm_blocks,
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clk => CLK_I,
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clk => CLK_I,
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cycle_wait_baud => baud_wait,
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cycle_wait_baud => baud_wait,
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byte_tx => data_byte_tx,
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byte_tx => data_byte_tx,
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