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reset : in std_logic; --synchronous reset
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reset : in std_logic; --synchronous reset
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--Serial UART
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--Serial UART
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i_rxd : in std_logic; --receive serial data (asynchronous)
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i_rxd : in std_logic; --receive serial data (asynchronous)
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o_txd : out std_logic; --transmit serial data
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o_txd : out std_logic; --transmit serial data
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--Cpu register interface
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--Cpu register interface
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i_addr : in std_logic_vector(15 downto 0); --highest index is msb of address.
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i_addr : in std_logic_vector; --highest index is msb of address.
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i_write_enable : in std_logic; --high for 1 clk period for a write
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i_write_enable : in std_logic; --high for 1 clk period for a write
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i_read_enable : in std_logic; --high for 1 clk period for a read
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i_read_enable : in std_logic; --high for 1 clk period for a read
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i_data : in std_logic_vector(7 downto 0);
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i_data : in std_logic_vector(7 downto 0);
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o_data : out std_logic_vector(7 downto 0) --data returned up to 2 clock cycles after read_enable
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o_data : out std_logic_vector(7 downto 0) --data returned up to 2 clock cycles after read_enable
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);
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);
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