URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] [code/] [ab_top.vhd] - Diff between revs 3 and 16

Rev 3	Rev 16
Line 55...	Line 55...
`--=============================================================================`	`--=============================================================================`

`entity ab_top is`	`entity ab_top is`
`port(`	`port(`
`clk_uart_29MHz_i : in std_logic;`	`clk_uart_29MHz_i : in std_logic;`
	`uart_rst_i : in std_logic;`
	`uart_leds_o : out std_logic_vector(7 downto 0);`
`clk_uart_monitor_o : out std_logic;`	`clk_uart_monitor_o : out std_logic;`
`-- #####################`	`-- #####################`
`-- ADD your registers toward the rest of the logic here`	`-- ADD your registers toward the rest of the logic here`
`-- #####################`	`-- #####################`
`uart_din_o : out std_logic;`	`uart_din_o : out std_logic;`