| Line 80... |
Line 80... |
sys_rst_i : in std_logic; -- system reset
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sys_rst_i : in std_logic; -- system reset
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-- TX/RX process command line
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-- TX/RX process command line
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echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
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echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
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tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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-- serial I/O side
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-- serial I/O side
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lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
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uart_din_i : in std_logic; -- Serial data INPUT signal (from the FPGA)
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lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
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uart_dout_o : out std_logic; -- Serial data OUTPUT signal (to the FPGA)
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cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
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-- parallel I/O side
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-- parallel I/O side
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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-- RX part/control
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-- RX part/control
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
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| Line 108... |
Line 107... |
-- generic signals
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-- generic signals
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signal s_rst : std_logic; -- main reset
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signal s_rst : std_logic; -- main reset
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signal s_clk_uart : std_logic; -- slow (29 MHz) clock
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signal s_clk_uart : std_logic; -- slow (29 MHz) clock
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-- uart control signals
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-- uart control signals
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signal s_uart_cp : std_logic_vector (2 downto 0); -- unused
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signal s_uart_br_clk : std_logic; -- unused clock monitor
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signal s_uart_br_clk : std_logic; -- unused clock monitor
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signal s_uart_rx_add : std_logic_vector (15 downto 0);
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signal s_uart_rx_add : std_logic_vector (15 downto 0);
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signal s_uart_rx_data : std_logic_vector (31 downto 0);
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signal s_uart_rx_data : std_logic_vector (31 downto 0);
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signal s_uart_rx_rdy : std_logic;
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signal s_uart_rx_rdy : std_logic;
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signal s_uart_rx_stb_read_data : std_logic;
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signal s_uart_rx_stb_read_data : std_logic;
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| Line 284... |
Line 282... |
port map(
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port map(
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sys_clk_i => s_clk_uart,
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sys_clk_i => s_clk_uart,
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sys_rst_i => s_rst,
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sys_rst_i => s_rst,
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echo_en_i => r_config_addr_uart(0),
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echo_en_i => r_config_addr_uart(0),
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tx_addr_wwo_i => r_config_addr_uart(1),
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tx_addr_wwo_i => r_config_addr_uart(1),
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lantronix_output_i => uart_dout_i,
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uart_dout_i => uart_dout_i,
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lantronix_input_o => uart_din_o,
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uart_din_o => uart_din_o,
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cp_b => s_uart_cp,
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s_br_clk_uart_o => s_uart_br_clk,
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s_br_clk_uart_o => s_uart_br_clk,
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v_rx_add_o => s_uart_rx_add,
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v_rx_add_o => s_uart_rx_add,
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v_rx_data_o => s_uart_rx_data,
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v_rx_data_o => s_uart_rx_data,
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s_rx_rdy_o => s_uart_rx_rdy,
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s_rx_rdy_o => s_uart_rx_rdy,
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s_rx_stb_read_data_i => s_uart_rx_stb_read_data,
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s_rx_stb_read_data_i => s_uart_rx_stb_read_data,
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