| Line 73... |
Line 73... |
sys_rst_i : in std_logic; -- system reset
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sys_rst_i : in std_logic; -- system reset
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-- TX/RX process command line
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-- TX/RX process command line
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echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
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echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
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tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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-- serial I/O side
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-- serial I/O side
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lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
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uart_din_i : in std_logic; -- Serial data INPUT signal (from the FPGA)
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lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
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uart_dout_o : out std_logic; -- Serial data OUTPUT signal (to the FPGA)
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cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
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-- parallel I/O side
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-- parallel I/O side
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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-- RX part/control
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-- RX part/control
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
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| Line 113... |
Line 112... |
CS : in std_logic; -- Chip select -> 1 Cycle long CS strobe = 1 data transaction (w/r)
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CS : in std_logic; -- Chip select -> 1 Cycle long CS strobe = 1 data transaction (w/r)
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WR : in std_logic; -- WRITE when HIGH with CS high | READ when LOW with CS high
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WR : in std_logic; -- WRITE when HIGH with CS high | READ when LOW with CS high
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ADD : in std_logic_vector(2 downto 0); -- ADDRESS BUS
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ADD : in std_logic_vector(2 downto 0); -- ADDRESS BUS
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D : in std_logic_vector(7 downto 0); -- Input DATA BUS and CONTROL BUS
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D : in std_logic_vector(7 downto 0); -- Input DATA BUS and CONTROL BUS
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sRX : in std_logic; -- Lantronix's OUTPUT
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sRX : in std_logic; -- uart's INPUT
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CTSn : in std_logic := '1';
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CTSn : in std_logic := '1';
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DSRn : in std_logic := '1';
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DSRn : in std_logic := '1';
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RIn : in std_logic := '1';
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RIn : in std_logic := '1';
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DCDn : in std_logic := '1';
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DCDn : in std_logic := '1';
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sTX : out std_logic; -- Lantronix's INPUT
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sTX : out std_logic; -- uart's OUTPUT
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DTRn : out std_logic;
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DTRn : out std_logic;
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RTSn : out std_logic;
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RTSn : out std_logic;
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OUT1n : out std_logic;
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OUT1n : out std_logic;
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OUT2n : out std_logic;
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OUT2n : out std_logic;
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TXRDYn : out std_logic; -- Tx FIFO not Full
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TXRDYn : out std_logic; -- Tx FIFO not Full
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| Line 339... |
Line 338... |
-- architecture begin
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-- architecture begin
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--=============================================================================
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--=============================================================================
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begin
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begin
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s_clk <= sys_clk_i; -- 14,xxx MHz main clock single ended buffer and division by one
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s_clk <= sys_clk_i; -- 29,xxx MHz main clock single ended buffer
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-- and 1 Mbit/s with Lantronix
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s_clk_n <= not s_clk;
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s_clk_n <= not s_clk;
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s_rst <= sys_rst_i;
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s_rst <= sys_rst_i;
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s_br_clk <= s_clk;
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s_br_clk <= s_clk;
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s_reading_proc <= v_lbus_state(1);
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s_reading_proc <= v_lbus_state(1);
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| Line 490... |
Line 489... |
rst_buffer => s_rst_buffer, -- soft fifo release reset after init
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rst_buffer => s_rst_buffer, -- soft fifo release reset after init
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CS => s_cs, -- Chip select -> 1 Cycle long CS strobe = 1 data transaction (w/r)
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CS => s_cs, -- Chip select -> 1 Cycle long CS strobe = 1 data transaction (w/r)
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WR => s_wr, -- WRITE when HIGH with CS high | READ when LOW with CS high
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WR => s_wr, -- WRITE when HIGH with CS high | READ when LOW with CS high
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ADD => uart_add_bus, -- ADDRESS BUS
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ADD => uart_add_bus, -- ADDRESS BUS
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D => uart_data_bus, -- Input DATA BUS and CONTROL BUS
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D => uart_data_bus, -- Input DATA BUS and CONTROL BUS
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sRX => lantronix_output_i, -- Lantronix's OUTPUT
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sRX => uart_din_i, -- uart' INPUT
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CTSn => '1', -- not used
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CTSn => '1', -- not used
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DSRn => '1', -- not used
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DSRn => '1', -- not used
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RIn => '1', -- not used
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RIn => '1', -- not used
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DCDn => '1', -- not used
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DCDn => '1', -- not used
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sTX => lantronix_input_o, -- Lantronix's INPUT
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sTX => uart_dout_o, -- uart's OUTPUT
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DTRn => open, -- not used
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DTRn => open, -- not used
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RTSn => open, -- not used
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RTSn => open, -- not used
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OUT1n => open, -- not used
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OUT1n => open, -- not used
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OUT2n => open, -- not used
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OUT2n => open, -- not used
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TXRDYn => uart_txrdy_n, -- Tx FIFO not Fully
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TXRDYn => uart_txrdy_n, -- Tx FIFO not Fully
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