URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] [code/] [ab_uart_lbus_slave.vhd] - Diff between revs 3 and 7

Rev 3	Rev 7
Line 354...	Line 354...
`v_data_init <= "10000011"; -- write FIFO Control Register`	`v_data_init <= "10000011"; -- write FIFO Control Register`
`s_slave_init <= WRITE_DIVLTC;`	`s_slave_init <= WRITE_DIVLTC;`
`when WRITE_DIVLTC => -- init WRITE_DIVLTC`	`when WRITE_DIVLTC => -- init WRITE_DIVLTC`
`if s_write_msb = '0' then`	`if s_write_msb = '0' then`
`v_add_init <= O"0"; -- init Divisor Latch lsb`	`v_add_init <= O"0"; -- init Divisor Latch lsb`
`v_data_init <= "00000010";--"00001111"; -- DEC 15 Baudrate = 230400 bps @ 55,296 MHz`	`v_data_init <= "00000010"; -- DEC 2 Baudrate = 921600 bps @ 29,4912 MHz`
`s_write_msb <= '1';`	`s_write_msb <= '1';`
`s_slave_init <= WRITE_DIVLTC;`	`s_slave_init <= WRITE_DIVLTC;`
`else`	`else`
`v_add_init <= O"1"; -- init Divisor Latch msb`	`v_add_init <= O"1"; -- init Divisor Latch msb`
`v_data_init <= "00000000";`	`v_data_init <= "00000000";`