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https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk
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Line 354... |
v_data_init <= "10000011"; -- write FIFO Control Register
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v_data_init <= "10000011"; -- write FIFO Control Register
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s_slave_init <= WRITE_DIVLTC;
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s_slave_init <= WRITE_DIVLTC;
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when WRITE_DIVLTC => -- init WRITE_DIVLTC
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when WRITE_DIVLTC => -- init WRITE_DIVLTC
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if s_write_msb = '0' then
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if s_write_msb = '0' then
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v_add_init <= O"0"; -- init Divisor Latch lsb
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v_add_init <= O"0"; -- init Divisor Latch lsb
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v_data_init <= "00000010";--"00001111"; -- DEC 15 Baudrate = 230400 bps @ 55,296 MHz
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v_data_init <= "00000010"; -- DEC 2 Baudrate = 921600 bps @ 29,4912 MHz
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s_write_msb <= '1';
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s_write_msb <= '1';
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s_slave_init <= WRITE_DIVLTC;
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s_slave_init <= WRITE_DIVLTC;
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else
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else
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v_add_init <= O"1"; -- init Divisor Latch msb
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v_add_init <= O"1"; -- init Divisor Latch msb
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v_data_init <= "00000000";
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v_data_init <= "00000000";
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