URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_uart_16550.vhd] - Diff between revs 3 and 19

Rev 3	Rev 19
Line 53...	Line 53...
`CS : in std_logic; -- Chip select -> 1 Cycle long CS strobe = 1 data send`	`CS : in std_logic; -- Chip select -> 1 Cycle long CS strobe = 1 data send`
`WR : in std_logic; -- WRITE when HIGH with CS high \| READ when LOW with CS high`	`WR : in std_logic; -- WRITE when HIGH with CS high \| READ when LOW with CS high`
`ADD : in std_logic_vector(2 downto 0); -- Address bus`	`ADD : in std_logic_vector(2 downto 0); -- Address bus`
`D : in std_logic_vector(7 downto 0); -- Input DATA BUS`	`D : in std_logic_vector(7 downto 0); -- Input DATA BUS`

`sRX : in std_logic; -- Lantronix's OUTPUT`	`sRX : in std_logic; -- uart's INPUT`
`CTSn : in std_logic := '1';`	`CTSn : in std_logic := '1';`
`DSRn : in std_logic := '1';`	`DSRn : in std_logic := '1';`
`RIn : in std_logic := '1';`	`RIn : in std_logic := '1';`
`DCDn : in std_logic := '1';`	`DCDn : in std_logic := '1';`

`sTX : out std_logic; -- Lantronix's INPUT`	`sTX : out std_logic; -- uart's OUTPUT`
`DTRn : out std_logic; -- not used`	`DTRn : out std_logic; -- not used`
`RTSn : out std_logic; -- not used`	`RTSn : out std_logic; -- not used`
`OUT1n : out std_logic; -- not used`	`OUT1n : out std_logic; -- not used`
`OUT2n : out std_logic; -- not used`	`OUT2n : out std_logic; -- not used`
`TXRDYn : out std_logic; -- Tx FIFO Data Ready`	`TXRDYn : out std_logic; -- Tx FIFO Data Ready`