URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] [code/] [testbenches/] [tb_UART_control.vhd] - Diff between revs 24 and 25

Rev 24	Rev 25
Line 97...	Line 97...
`X"50", -- BYTE2`	`X"50", -- BYTE2`
`X"08", -- BYTE3`	`X"08", -- BYTE3`
`X"40", -- BYTE4`	`X"40", -- BYTE4`
`X"80", -- BYTE5`	`X"80", -- BYTE5`
`X"20", -- BYTE6`	`X"20", -- BYTE6`
	`-- ##############`
	`-- add other data`
	`-- ##############`
`-- 7th data`	`-- 7th data`
`X"80", -- BYTE1`	`X"80", -- BYTE1`
`X"00", -- BYTE2`	`X"00", -- BYTE2`
`X"00", -- BYTE3`	`X"00", -- BYTE3`
`X"00", -- BYTE4`	`X"00", -- BYTE4`
`X"00", -- BYTE5`	`X"00", -- BYTE5`
`X"00" -- BYTE6`	`X"00" -- BYTE6`
`-- add other data`
`);`	`);`

`BEGIN`	`BEGIN`

`-- Instantiate the Unit Under Test (UUT)`	`-- Instantiate the Unit Under Test (UUT)`