URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] [documents/] [OpenCores_description.txt] - Diff between revs 14 and 27

Rev 14	Rev 27
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`Almost no documentation is required.`	`Almost no documentation is required.`
`no knowledge of the internals of the core required.`	`no knowledge of the internals of the core required.`
`The top entity is self-explanatory.`	`The top entity is self-explanatory.`

`Use RealTerm to simply send and receive HEX commands ( http://realterm.sourceforge.net/ ).`	`Remotely control the logic from a PC:`
`TCP/IP to UART bridging is just around the corner.`	`~ Under Windows use RealTerm to simply send and receive HEX commands ( http://realterm.sourceforge.net/ ).`
	`~ TCP/IP to UART bridging is just around the corner using inexpensive external devices.`

`crossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). Tested up to 1 Mbps with a 29.4912 MHz oscillator.`	`crossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). Tested up to 1 Mbps with a 29.4912 MHz oscillator.`

`## Feeback:`	`## Feeback:`
`Give comments and feedback using the official core thread on the OpenCores forum:`	`Give comments and feedback using the official core thread on the OpenCores forum:`