URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] [documents/] [OpenCores_description.txt] - Diff between revs 27 and 29

Rev 27	Rev 29
Line 22...	Line 22...
`no knowledge of the internals of the core required.`	`no knowledge of the internals of the core required.`
`The top entity is self-explanatory.`	`The top entity is self-explanatory.`

`Remotely control the logic from a PC:`	`Remotely control the logic from a PC:`
`~ Under Windows use RealTerm to simply send and receive HEX commands ( http://realterm.sourceforge.net/ ).`	`~ Under Windows use RealTerm to simply send and receive HEX commands ( http://realterm.sourceforge.net/ ).`
	`~ Simple Python script to drive the uart via command line in linux (see software details tab above).`
`~ TCP/IP to UART bridging is just around the corner using inexpensive external devices.`	`~ TCP/IP to UART bridging is just around the corner using inexpensive external devices.`


`crossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). Tested up to 1 Mbps with a 29.4912 MHz oscillator.`	`crossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). Tested up to 1 Mbps with a 29.4912 MHz oscillator.`


`## Feeback:`	`## Feeback:`
`Give comments and feedback using the official core thread on the OpenCores forum:`	`Give comments and feedback using the official core thread on the OpenCores forum:`
`http://opencores.org/forum,Cores,0,4443`
`No newline at end of file`	`No newline at end of file`