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https://opencores.org/ocsvn/uart_observer/uart_observer/trunk
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module uart_observer (
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module uart_observer (
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// clock, tested with 90 MHZ clock
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// clock, tested with 90 MHZ clock
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input clk,
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input CLK_I,
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// The array of observables.
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// The array of observables.
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input wire [BITS-1:0] observables,
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input wire [BITS-1:0] DAT_I,
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// UART
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// UART
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input CTS, // "clear to send"
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input CTS, // "clear to send"
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output TXD, // Serial data output
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output TXD, // Serial data output
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else
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else
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phase <= phase + 1;
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phase <= phase + 1;
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end
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end
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endtask
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endtask
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always @(posedge clk)
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always @(posedge CLK_I)
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begin :cl
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begin :cl
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// Need 781.25 (90000000 Hz to 115200 Hz)
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// Need 781.25 (90000000 Hz to 115200 Hz)
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if (divider > DIV_MAX)
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if (divider > DIV_MAX)
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begin
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begin
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if (phase == 0 && ram_addr == 0)
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if (phase == 0 && ram_addr == 0)
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begin
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begin
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observables_reg = observables;
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observables_reg = DAT_I;
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if (observables_prev == observables_reg)
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if (observables_prev == observables_reg)
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begin
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begin
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r_reg <= 10'b1_1111_1111_1;
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r_reg <= 10'b1_1111_1111_1;
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divider <= 0;
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divider <= 0;
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sending <= 0;
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sending <= 0;
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