URL https://opencores.org/ocsvn/uart_observer/uart_observer/trunk

Subversion Repositories uart_observer

[/] [uart_observer/] [trunk/] [verilog/] [uart_observer.v] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 10...	Line 10...
`//`	`//`
`//////////////////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////////////////`

`module uart_observer (`	`module uart_observer (`
`// clock, tested with 90 MHZ clock`	`// clock, tested with 90 MHZ clock`
`input clk,`	`input CLK_I,`

`// The array of observables.`	`// The array of observables.`
`input wire [BITS-1:0] observables,`	`input wire [BITS-1:0] DAT_I,`

`// UART`	`// UART`
`input CTS, // "clear to send"`	`input CTS, // "clear to send"`

`output TXD, // Serial data output`	`output TXD, // Serial data output`
Line 201...	Line 201...
`else`	`else`
`phase <= phase + 1;`	`phase <= phase + 1;`
`end`	`end`
`endtask`	`endtask`

`always @(posedge clk)`	`always @(posedge CLK_I)`
`begin :cl`	`begin :cl`
`// Need 781.25 (90000000 Hz to 115200 Hz)`	`// Need 781.25 (90000000 Hz to 115200 Hz)`
`if (divider > DIV_MAX)`	`if (divider > DIV_MAX)`
`begin`	`begin`
`if (phase == 0 && ram_addr == 0)`	`if (phase == 0 && ram_addr == 0)`
`begin`	`begin`
`observables_reg = observables;`	`observables_reg = DAT_I;`
`if (observables_prev == observables_reg)`	`if (observables_prev == observables_reg)`
`begin`	`begin`
`r_reg <= 10'b1_1111_1111_1;`	`r_reg <= 10'b1_1111_1111_1;`
`divider <= 0;`	`divider <= 0;`
`sending <= 0;`	`sending <= 0;`