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[/] [uart_observer/] [trunk/] [verilog/] [uart_observer_demonstrator.v] - Diff between revs 3 and 4

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/**
/**
* Demonstrates the functionality of the UART observer.  Shows the 64 bits of
* Demonstrates the functionality of the UART observer. Reads 64 bits from the terminal keyboard.
* binary data that, in this demo, are derived from push buttons and dip switches on FPGA board.
 
*/
*/
module uart_observer_demonstrator (
module uart_observer_demonstrator (
  input USB_UART_TX_FPGA_RX_LS,
  input USB_UART_TX_FPGA_RX_LS,
  input USB_UART_CTS_I_B_LS,
  input USB_UART_CTS_I_B_LS,
  input CLK_I,
  input CLK_I,
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  output USB_UART_RX_FPGA_TX_LS,
  output USB_UART_RX_FPGA_TX_LS,
  output USB_UART_RTS_O_B_LS
  output USB_UART_RTS_O_B_LS
);
);
 
 
 // 64 bits we observe.
 // 32 bits we observe.
 wire [63:0] observables;
 wire [31:0] observables;
 
 
 // Observe the switches as example
 uart_receiver #(.CLOCK_FREQ (90_000_000), .BAUDS(921600), .BITS(32) )
 // First byte
 UR(
 
  // Clock
 assign observables[0] = GPIO_SW_E;
  .CLK_I(CLK_I),
 assign observables[1] = GPIO_SW_W;
 
 assign observables[2] = GPIO_SW_S;
 
 assign observables[3] = GPIO_SW_N;
 
 
 
 assign observables[4] = GPIO_SW_E;
 
 assign observables[5] = GPIO_SW_W;
 
 assign observables[6] = GPIO_SW_S;
 
 assign observables[7] = GPIO_SW_N;
 
 
 
 // Second
 
 
 
 assign observables[8] = GPIO_SW_E;
 
 assign observables[9] = GPIO_SW_W;
 
 assign observables[10] = GPIO_SW_S;
 
 assign observables[11] = GPIO_SW_N;
 
 
 
 assign observables[12] = GPIO_SW_E;
 
 assign observables[13] = GPIO_SW_W;
 
 assign observables[14] = GPIO_SW_S;
 
 assign observables[15] = GPIO_SW_N;
 
 
 
 // Third
 
 
 
 assign observables[16] = GPIO_DIP_SW0;
 
 assign observables[17] = GPIO_DIP_SW1;
 
 assign observables[18] = GPIO_DIP_SW2;
 
 assign observables[19] = GPIO_DIP_SW3;
 
 
 
 assign observables[20] = GPIO_DIP_SW3;
 
 assign observables[21] = GPIO_DIP_SW2;
 
 assign observables[22] = GPIO_DIP_SW1;
 
 assign observables[23] = GPIO_DIP_SW0;
 
 
 
 // Forth
 
 
 
 assign observables[24] = GPIO_SW_E;
 
 assign observables[25] = GPIO_SW_W;
 
 assign observables[26] = GPIO_SW_S;
 
 assign observables[27] = GPIO_SW_N;
 
 
 
 assign observables[28] = GPIO_SW_E;
  // Values to observer
 assign observables[29] = GPIO_SW_W;
  .DAT_O(observables),
 assign observables[30] = GPIO_SW_S;
 
 assign observables[31] = GPIO_SW_N;
 
 
 
 assign observables[63] = GPIO_SW_C;
  // UART
 
  .RXD(USB_UART_TX_FPGA_RX_LS), // data  
 
  .CTR(USB_UART_CTS_I_B_LS)     // clear to receive
 
 );
 
 
 uart_observer #(.CLOCK_FREQ (90_000_000), .BAUDS(921600), .BITS(64) )
 uart_observer #(.CLOCK_FREQ (90_000_000), .BAUDS(921600), .BITS(32) )
 U0(
 U0(
  // Clock
  // Clock
  .CLK_I(CLK_I),
  .CLK_I(CLK_I),
 
 
  // Values to observer
  // Values to observer
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 assign GPIO_LED_1 = observables[1];
 assign GPIO_LED_1 = observables[1];
 assign GPIO_LED_2 = observables[2];
 assign GPIO_LED_2 = observables[2];
 assign GPIO_LED_3 = observables[3];
 assign GPIO_LED_3 = observables[3];
 assign GPIO_LED_4 = observables[4];
 assign GPIO_LED_4 = observables[4];
 
 
 
 
endmodule
endmodule
 
 
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