| Line 18... |
Line 18... |
-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Revision 0.02 - fixed up setting of tx_result control defaults
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-- Revision 0.02 - fixed up setting of tx_result control defaults
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-- Revision 0.03 - Added data_out_first
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-- Revision 0.03 - Added data_out_first
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-- Revision 0.04 - Added handling of broadcast address
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-- Revision 0.04 - Added handling of broadcast address
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-- Revision 0.05 - Fix cks calc when add of high bits causes another ovf
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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| Line 66... |
Line 67... |
SEND_ETH_HDR, -- sending the ethernet header
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SEND_ETH_HDR, -- sending the ethernet header
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SEND_IP_HDR, -- sending the IP header
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SEND_IP_HDR, -- sending the IP header
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SEND_USER_DATA -- sending the users data
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SEND_USER_DATA -- sending the users data
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);
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);
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type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, FINAL, WAIT_END);
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type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END);
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type count_mode_type is (RST, INCR, HOLD);
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type count_mode_type is (RST, INCR, HOLD);
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type settable_cnt_type is (RST, SET, INCR, HOLD);
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type settable_cnt_type is (RST, SET, INCR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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| Line 523... |
Line 524... |
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
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tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
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crc_state <= DAL;
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crc_state <= DAL;
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when DAL =>
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when DAL =>
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tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
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tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
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crc_state <= ADDOVF;
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when ADDOVF =>
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tx_hdr_cks <= std_logic_vector ((unsigned(tx_hdr_cks) and x"00ffff")+ unsigned(tx_hdr_cks(23 downto 16)));
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crc_state <= FINAL;
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crc_state <= FINAL;
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when FINAL =>
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when FINAL =>
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tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
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tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
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crc_state <= WAIT_END;
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crc_state <= WAIT_END;
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