| Line 26... |
Line 26... |
use work.arp_types.all;
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use work.arp_types.all;
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entity UDP_Complete is
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entity UDP_Complete is
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generic (
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generic (
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
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ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
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ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
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);
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);
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Port (
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Port (
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-- UDP TX signals
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-- UDP TX signals
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_txi : in udp_tx_type; -- UDP tx cxns
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udp_txi : in udp_tx_type; -- UDP tx cxns
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| Line 66... |
Line 68... |
gmii_crs : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic
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mii_tx_clk : in std_logic
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);
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);
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end UDP_Complete;
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end UDP_Complete;
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architecture structural of UDP_Complete is
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architecture structural of UDP_Complete is
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Component Declaration for UDP complete no mac
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-- Component Declaration for UDP complete no mac
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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COMPONENT UDP_Complete_nomac
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COMPONENT UDP_Complete_nomac
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generic (
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generic (
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
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ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
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ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
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);
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);
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Port (
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Port (
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-- UDP TX signals
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-- UDP TX signals
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_txi : in udp_tx_type; -- UDP tx cxns
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udp_txi : in udp_tx_type; -- UDP tx cxns
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| Line 116... |
Line 123... |
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Component Declaration for the MAC layer
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-- Component Declaration for the MAC layer
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component mac_layer
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component mac_v2_2
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-- component xv6mac_straight
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port (
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port (
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-- System controls
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-- System controls
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------------------
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------------------
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glbl_rst : in std_logic; -- asynchronous reset
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glbl_rst : in std_logic; -- asynchronous reset
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mac_reset : in std_logic; -- reset mac layer
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mac_reset : in std_logic; -- reset mac layer
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| Line 196... |
Line 204... |
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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udp_block: UDP_Complete_nomac
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udp_block: UDP_Complete_nomac
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generic map (
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generic map (
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CLOCK_FREQ => CLOCK_FREQ,
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CLOCK_FREQ => CLOCK_FREQ,
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ARP_TIMEOUT => ARP_TIMEOUT
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ARP_TIMEOUT => ARP_TIMEOUT,
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ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
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MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
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)
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)
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PORT MAP (
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PORT MAP (
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-- UDP TX signals
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-- UDP TX signals
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udp_tx_start => udp_tx_start,
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udp_tx_start => udp_tx_start,
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udp_txi => udp_txi,
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udp_txi => udp_txi,
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| Line 236... |
Line 246... |
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Instantiate the MAC layer
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-- Instantiate the MAC layer
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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mac_block : mac_layer
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mac_block : mac_v2_2
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-- mac_block : xv6mac_straight
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Port map(
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Port map(
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-- System controls
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-- System controls
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------------------
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------------------
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glbl_rst => reset,
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glbl_rst => reset,
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mac_reset => '0',
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mac_reset => '0',
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Line 292... |
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end structural;
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end structural;
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