| Line 33... |
Line 33... |
clk_in_n : in std_logic;
|
clk_in_n : in std_logic;
|
|
|
-- System controls
|
-- System controls
|
------------------
|
------------------
|
PBTX : in std_logic;
|
PBTX : in std_logic;
|
|
PB_DO_SECOND_TX : in std_logic;
|
|
DO_SECOND_TX_LED : out std_logic;
|
UDP_RX : out std_logic;
|
UDP_RX : out std_logic;
|
UDP_Start : out std_logic;
|
UDP_Start : out std_logic;
|
PBTX_LED : out std_logic;
|
PBTX_LED : out std_logic;
|
TX_Started : out std_logic;
|
TX_Started : out std_logic;
|
TX_Completed : out std_logic;
|
TX_Completed : out std_logic;
|
| Line 62... |
Line 64... |
);
|
);
|
end UDP_integration_example;
|
end UDP_integration_example;
|
|
|
architecture Behavioral of UDP_integration_example is
|
architecture Behavioral of UDP_integration_example is
|
|
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Component Declaration for the complete IP layer
|
-- Component Declaration for the complete UDP layer
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
component UDP_Complete
|
component UDP_Complete
|
generic (
|
generic (
|
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
|
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
|
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
|
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
|
|
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
|
|
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
|
);
|
);
|
Port (
|
Port (
|
-- UDP TX signals
|
-- UDP TX signals
|
udp_tx_start : in std_logic; -- indicates req to tx UDP
|
udp_tx_start : in std_logic; -- indicates req to tx UDP
|
udp_txi : in udp_tx_type; -- UDP tx cxns
|
udp_txi : in udp_tx_type; -- UDP tx cxns
|
| Line 108... |
Line 113... |
gmii_crs : in std_logic;
|
gmii_crs : in std_logic;
|
mii_tx_clk : in std_logic
|
mii_tx_clk : in std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp;
|
|
|
|
|
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);
|
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR);
|
type count_mode_type is (RST, INCR, HOLD);
|
type count_mode_type is (RST, INCR, HOLD);
|
type set_clr_type is (SET, CLR, HOLD);
|
type set_clr_type is (SET, CLR, HOLD);
|
|
type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD);
|
|
|
-- system signals
|
-- system signals
|
signal clk_int : std_logic;
|
signal clk_int : std_logic;
|
signal our_mac : STD_LOGIC_VECTOR (47 downto 0);
|
signal our_mac : STD_LOGIC_VECTOR (47 downto 0);
|
signal our_ip : STD_LOGIC_VECTOR (31 downto 0);
|
signal our_ip : STD_LOGIC_VECTOR (31 downto 0);
|
| Line 134... |
Line 142... |
signal count : unsigned (7 downto 0);
|
signal count : unsigned (7 downto 0);
|
signal tx_hdr : udp_tx_header_type;
|
signal tx_hdr : udp_tx_header_type;
|
signal tx_start_reg : std_logic;
|
signal tx_start_reg : std_logic;
|
signal tx_started_reg : std_logic;
|
signal tx_started_reg : std_logic;
|
signal tx_fin_reg : std_logic;
|
signal tx_fin_reg : std_logic;
|
|
signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first
|
|
signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx
|
|
|
-- control signals
|
-- control signals
|
signal next_state : state_type;
|
signal next_state : state_type;
|
signal set_state : std_logic;
|
signal set_state : std_logic;
|
signal set_count : count_mode_type;
|
signal set_count : count_mode_type;
|
| Line 146... |
Line 156... |
signal set_last : std_logic;
|
signal set_last : std_logic;
|
signal set_tx_started : set_clr_type;
|
signal set_tx_started : set_clr_type;
|
signal set_tx_fin : set_clr_type;
|
signal set_tx_fin : set_clr_type;
|
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
|
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
|
signal control_int : udp_control_type;
|
signal control_int : udp_control_type;
|
|
signal set_second_tx : sec_tx_ctrl_type;
|
|
|
begin
|
begin
|
|
|
process (
|
process (
|
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
|
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
|
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
|
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
|
reset, tx_started_reg, tx_fin_reg, tx_start_reg
|
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx,
|
|
PB_DO_SECOND_TX, do_second_tx
|
)
|
)
|
begin
|
begin
|
-- set up our local addresses and default controls
|
-- set up our local addresses and default controls
|
our_ip <= x"c0a80509"; -- 192.168.5.9
|
our_ip <= x"c0a80019"; -- 192.168.0.25
|
our_mac <= x"002320212223";
|
our_mac <= x"002320212223";
|
control_int.ip_controls.arp_controls.clear_cache <= '0';
|
control_int.ip_controls.arp_controls.clear_cache <= '0';
|
|
|
-- determine RX good and error LEDs
|
-- determine RX good and error LEDs
|
if udp_rx_int.hdr.is_valid = '1' then
|
if udp_rx_int.hdr.is_valid = '1' then
|
| Line 172... |
Line 184... |
UDP_Start <= udp_rx_start_int;
|
UDP_Start <= udp_rx_start_int;
|
TX_Started <= tx_start_reg; --tx_started_reg;
|
TX_Started <= tx_start_reg; --tx_started_reg;
|
TX_Completed <= tx_fin_reg;
|
TX_Completed <= tx_fin_reg;
|
TX_RSLT_0 <= udp_tx_result_int(0);
|
TX_RSLT_0 <= udp_tx_result_int(0);
|
TX_RSLT_1 <= udp_tx_result_int(1);
|
TX_RSLT_1 <= udp_tx_result_int(1);
|
|
DO_SECOND_TX_LED <= prime_second_tx;
|
|
|
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
|
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
|
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
|
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
|
|
|
-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
|
-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
|
case state is
|
case state is
|
when IDLE => display (3 downto 0) <= "0001";
|
when IDLE => display (3 downto 0) <= "0001";
|
when WAIT_RX_DONE => display (3 downto 0) <= "0010";
|
when WAIT_RX_DONE => display (3 downto 0) <= "0010";
|
when DATA_OUT => display (3 downto 0) <= "0011";
|
when DATA_OUT => display (3 downto 0) <= "0011";
|
|
when PAUSE => display (3 downto 0) <= "0100";
|
|
when CHECK_SECOND_TX => display (3 downto 0) <= "0101";
|
|
when SET_SEC_HDR => display (3 downto 0) <= "0110";
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
|
|
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
|
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
|
|
|
-- TX response process - COMB
|
-- TX response process - COMB
|
tx_proc_combinatorial: process(
|
tx_proc_combinatorial: process(
|
-- inputs
|
-- inputs
|
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
|
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
|
udp_tx_int.data.data_out_valid, PBTX,
|
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX,
|
-- state
|
-- state
|
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
|
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx,
|
-- controls
|
-- controls
|
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
|
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
|
set_tx_started, set_tx_fin, first_byte_rx
|
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx
|
)
|
)
|
begin
|
begin
|
-- set output_followers
|
-- set output_followers
|
udp_tx_int.hdr <= tx_hdr;
|
udp_tx_int.hdr <= tx_hdr;
|
udp_tx_int.data.data_out_last <= set_last;
|
udp_tx_int.data.data_out_last <= set_last;
|
| Line 216... |
Line 232... |
set_tx_started <= HOLD;
|
set_tx_started <= HOLD;
|
set_tx_fin <= HOLD;
|
set_tx_fin <= HOLD;
|
first_byte_rx <= (others => '0');
|
first_byte_rx <= (others => '0');
|
udp_tx_int.data.data_out <= (others => '0');
|
udp_tx_int.data.data_out <= (others => '0');
|
udp_tx_int.data.data_out_valid <= '0';
|
udp_tx_int.data.data_out_valid <= '0';
|
|
set_second_tx <= HOLD;
|
|
|
|
if PB_DO_SECOND_TX = '1' then
|
|
set_second_tx <= PRIME;
|
|
end if;
|
|
|
-- FSM
|
-- FSM
|
case state is
|
case state is
|
|
|
when IDLE =>
|
when IDLE =>
|
| Line 257... |
Line 278... |
if udp_tx_result_int = UDPTX_RESULT_ERR then
|
if udp_tx_result_int = UDPTX_RESULT_ERR then
|
-- have an error from the IP TX layer, clear down the TX
|
-- have an error from the IP TX layer, clear down the TX
|
set_tx_start <= CLR;
|
set_tx_start <= CLR;
|
set_tx_fin <= SET;
|
set_tx_fin <= SET;
|
set_tx_started <= CLR;
|
set_tx_started <= CLR;
|
|
set_second_tx <= CLR;
|
next_state <= IDLE;
|
next_state <= IDLE;
|
set_state <= '1';
|
set_state <= '1';
|
else
|
else
|
if udp_tx_result_int = UDPTX_RESULT_SENDING then
|
if udp_tx_result_int = UDPTX_RESULT_SENDING then
|
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending
|
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending
|
| Line 274... |
Line 296... |
if udp_tx_data_out_ready_int = '1' then
|
if udp_tx_data_out_ready_int = '1' then
|
if unsigned(count) = x"03" then
|
if unsigned(count) = x"03" then
|
set_last <= '1';
|
set_last <= '1';
|
set_tx_fin <= SET;
|
set_tx_fin <= SET;
|
set_tx_started <= CLR;
|
set_tx_started <= CLR;
|
next_state <= IDLE;
|
next_state <= PAUSE;
|
set_state <= '1';
|
set_state <= '1';
|
else
|
else
|
set_count <= INCR;
|
set_count <= INCR;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
when PAUSE =>
|
|
next_state <= CHECK_SECOND_TX;
|
|
set_state <= '1';
|
|
|
|
|
|
when CHECK_SECOND_TX =>
|
|
if prime_second_tx = '1' then
|
|
set_second_tx <= DO;
|
|
next_state <= SET_SEC_HDR;
|
|
set_state <= '1';
|
|
else
|
|
set_second_tx <= CLR;
|
|
next_state <= IDLE;
|
|
set_state <= '1';
|
|
end if;
|
|
|
|
when SET_SEC_HDR =>
|
|
set_hdr <= '1';
|
|
set_tx_started <= SET;
|
|
set_tx_start <= SET;
|
|
next_state <= DATA_OUT;
|
|
set_state <= '1';
|
|
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
|
|
|
|
| Line 304... |
Line 349... |
tx_hdr.data_length <= (others => '0');
|
tx_hdr.data_length <= (others => '0');
|
tx_hdr.checksum <= (others => '0');
|
tx_hdr.checksum <= (others => '0');
|
tx_started_reg <= '0';
|
tx_started_reg <= '0';
|
tx_fin_reg <= '0';
|
tx_fin_reg <= '0';
|
PBTX_LED <= '0';
|
PBTX_LED <= '0';
|
|
do_second_tx <= '0';
|
|
prime_second_tx <= '0';
|
else
|
else
|
PBTX_LED <= PBTX;
|
PBTX_LED <= PBTX;
|
|
|
-- Next rx_state processing
|
-- Next rx_state processing
|
if set_state = '1' then
|
if set_state = '1' then
|
| Line 323... |
Line 370... |
when HOLD => count <= count;
|
when HOLD => count <= count;
|
end case;
|
end case;
|
|
|
-- set tx hdr
|
-- set tx hdr
|
if set_hdr = '1' then
|
if set_hdr = '1' then
|
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
|
-- select the dst addr of the tx:
|
if first_byte_rx = x"42" then
|
-- if do_second_tx, to solaris box
|
|
-- otherwise control according to first byte of received data:
|
|
-- B = broadcast
|
|
-- C = to dummy address to test timeout
|
|
-- D to solaris box
|
|
-- otherwise, direct to sender
|
|
if do_second_tx = '1' then
|
|
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
|
|
elsif first_byte_rx = x"42" then
|
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
|
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
|
elsif first_byte_rx = x"43" then
|
elsif first_byte_rx = x"43" then
|
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
|
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
|
|
elsif first_byte_rx = x"44" then
|
|
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
|
else
|
else
|
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
|
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
|
end if;
|
end if;
|
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
|
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
|
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
|
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
|
| Line 360... |
Line 417... |
when SET => tx_fin_reg <= '1';
|
when SET => tx_fin_reg <= '1';
|
when CLR => tx_fin_reg <= '0';
|
when CLR => tx_fin_reg <= '0';
|
when HOLD => tx_fin_reg <= tx_fin_reg;
|
when HOLD => tx_fin_reg <= tx_fin_reg;
|
end case;
|
end case;
|
|
|
|
-- set do_second_tx
|
|
case set_second_tx is
|
|
when PRIME =>
|
|
prime_second_tx <= '1';
|
|
when DO =>
|
|
prime_second_tx <= '0';
|
|
do_second_tx <= '1';
|
|
when CLR =>
|
|
prime_second_tx <= '0';
|
|
do_second_tx <= '0';
|
|
when HOLD =>
|
|
prime_second_tx <= prime_second_tx;
|
|
do_second_tx <= do_second_tx;
|
|
end case;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
| Line 373... |
Line 444... |
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Instantiate the UDP layer
|
-- Instantiate the UDP layer
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
UDP_block : UDP_Complete
|
UDP_block : UDP_Complete
|
generic map (
|
generic map (
|
ARP_TIMEOUT => 30 -- timeout in seconds
|
ARP_TIMEOUT => 10 -- timeout in seconds
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
-- UDP interface
|
-- UDP interface
|
udp_tx_start => udp_tx_start_int,
|
udp_tx_start => udp_tx_start_int,
|
udp_txi => udp_tx_int,
|
udp_txi => udp_tx_int,
|
