| Line 139... |
Line 139... |
signal set_tx_start : set_clr_type;
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signal set_tx_start : set_clr_type;
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signal set_last : std_logic;
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signal set_last : std_logic;
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signal set_tx_started : set_clr_type;
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signal set_tx_started : set_clr_type;
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signal set_tx_fin : set_clr_type;
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signal set_tx_fin : set_clr_type;
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signal set_udp_rx_start_reg : set_clr_type;
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signal set_udp_rx_start_reg : set_clr_type;
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signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
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begin
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begin
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process (
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process (
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our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
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our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
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| Line 169... |
Line 170... |
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
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display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
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display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
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display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
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end process;
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end process;
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-- AUTO TX process - on receipt of any UDP pkt, send a response
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-- AUTO TX process - on receipt of any UDP pkt, send a response,
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-- TX response process - COMB
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-- TX response process - COMB
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tx_proc_combinatorial: process(
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tx_proc_combinatorial: process(
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-- inputs
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-- inputs
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udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX, reset_leds,
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udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid,
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udp_rx_int, PBTX, reset_leds,
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-- state
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-- state
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state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
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state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
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-- controls
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-- controls
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next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
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next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
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set_tx_started, set_tx_fin, set_udp_rx_start_reg
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set_tx_started, set_tx_fin, set_udp_rx_start_reg, first_byte_rx
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)
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)
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begin
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begin
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-- set output_followers
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-- set output_followers
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udp_tx_int.hdr <= tx_hdr;
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udp_tx_int.hdr <= tx_hdr;
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udp_tx_int.data.data_out_last <= set_last;
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udp_tx_int.data.data_out_last <= set_last;
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| Line 197... |
Line 199... |
set_tx_start <= HOLD;
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set_tx_start <= HOLD;
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set_last <= '0';
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set_last <= '0';
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set_tx_started <= HOLD;
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set_tx_started <= HOLD;
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set_tx_fin <= HOLD;
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set_tx_fin <= HOLD;
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set_udp_rx_start_reg <= HOLD;
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set_udp_rx_start_reg <= HOLD;
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first_byte_rx <= (others => '0');
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-- FSM
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-- FSM
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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udp_tx_int.data.data_out <= (others => '0');
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udp_tx_int.data.data_out <= (others => '0');
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udp_tx_int.data.data_out_valid <= '0';
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udp_tx_int.data.data_out_valid <= '0';
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if udp_rx_start_int = '1' or PBTX = '1' then
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if udp_rx_start_int = '1' or PBTX = '1' then
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if udp_rx_start_int = '1' then
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first_byte_rx <= udp_rx_int.data.data_in;
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else
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first_byte_rx <= x"00";
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end if;
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set_udp_rx_start_reg <= SET;
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set_udp_rx_start_reg <= SET;
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set_tx_started <= SET;
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set_tx_started <= SET;
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set_hdr <= '1';
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set_hdr <= '1';
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set_tx_start <= SET;
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set_tx_start <= SET;
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set_tx_fin <= CLR;
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set_tx_fin <= CLR;
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| Line 276... |
Line 284... |
when HOLD => count <= count;
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when HOLD => count <= count;
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end case;
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end case;
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-- set tx hdr
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-- set tx hdr
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if set_hdr = '1' then
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if set_hdr = '1' then
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-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
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if first_byte_rx = x"42" then
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tx_hdr.dst_ip_addr <= IP_BC_ADDR;
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else
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tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
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tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
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end if;
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tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
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tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
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tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
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tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
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tx_hdr.data_length <= x"0004";
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tx_hdr.data_length <= x"0004";
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tx_hdr.checksum <= x"0000";
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tx_hdr.checksum <= x"0000";
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else
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else
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