This IP core converts from the UTMI interface to the reduced pin-count ULPI interface.
This IP core converts from the UTMI interface to the reduced pin-count ULPI interface.
This enables interfacing from a standard USB SIE with UTMI interface to a USB 2.0 PHY.
This enables interfacing from a standard USB SIE with UTMI interface to a USB 2.0 PHY.
This enables support of USB LS (1.5mbps), FS (12mbps) and HS (480mbps) transfers.
This enables support of USB LS (1.5mbps), FS (12mbps) and HS (480mbps) transfers.
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##### Testing
##### Testing
Verified under simulation and also on a Xilinx FPGA connected to a SMSC/Microchip USB3300 in device mode using the [USB3300 USB HS](http://www.waveshare.com/usb3300-usb-hs-board.htm) evaluation board.
Verified under simulation and also on a Xilinx FPGA connected to a SMSC/Microchip USB3300 in device mode using the [USB3300 USB HS](http://www.waveshare.com/usb3300-usb-hs-board.htm) evaluation board.
The supplied trivial testbench works with the free version of Modelsim.
The supplied testbench requires the SystemC libraries and Icarus Verilog, both of which are available for free.
##### Size / Performance
##### Size / Performance
With the current configuration...
With the current configuration...
* the design contains 67 flops, uses 46 slices (59 LUTs on a Xilinx Spartan 6 with IOB packing for the outputs).
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* This design consumes around 88 LUTs on a Xilinx Spartan 6 with IOB packing for the outputs.
