| Line 1... |
Line 1... |
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// ULPI (Link) Wrapper
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// ULPI (Link) Wrapper
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// V0.1
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// V1.0
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2015
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// Copyright 2015-2018
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: GPL
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// License: GPL
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// If you would like a version with a more permissive license for
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// If you would like a version with a more permissive license for
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| Line 40... |
Line 40... |
module ulpi_wrapper
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module ulpi_wrapper
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(
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(
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// ULPI Interface (PHY)
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// ULPI Interface (PHY)
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input ulpi_clk60_i,
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input ulpi_clk60_i,
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input ulpi_rst_i,
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input ulpi_rst_i,
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input [7:0] ulpi_data_i,
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input [7:0] ulpi_data_out_i,
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output [7:0] ulpi_data_o,
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output [7:0] ulpi_data_in_o,
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input ulpi_dir_i,
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input ulpi_dir_i,
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input ulpi_nxt_i,
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input ulpi_nxt_i,
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output ulpi_stp_o,
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output ulpi_stp_o,
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|
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// Register access (Wishbone pipelined access type)
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// NOTE: Tie inputs to 0 if unused
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input [7:0] reg_addr_i,
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input reg_stb_i,
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input reg_we_i,
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input [7:0] reg_data_i,
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output [7:0] reg_data_o,
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output reg_ack_o,
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// UTMI Interface (SIE)
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// UTMI Interface (SIE)
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input utmi_txvalid_i,
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input utmi_txvalid_i,
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output utmi_txready_o,
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output utmi_txready_o,
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output utmi_rxvalid_o,
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output utmi_rxvalid_o,
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output utmi_rxactive_o,
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output utmi_rxactive_o,
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output utmi_rxerror_o,
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output utmi_rxerror_o,
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output [7:0] utmi_data_o,
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output [7:0] utmi_data_in_o,
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input [7:0] utmi_data_i,
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input [7:0] utmi_data_out_i,
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input [1:0] utmi_xcvrselect_i,
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input [1:0] utmi_xcvrselect_i,
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input utmi_termselect_i,
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input utmi_termselect_i,
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input [1:0] utmi_opmode_i,
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input [1:0] utmi_op_mode_i,
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input utmi_dppulldown_i,
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input utmi_dppulldown_i,
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input utmi_dmpulldown_i,
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input utmi_dmpulldown_i,
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output [1:0] utmi_linestate_o
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output [1:0] utmi_linestate_o
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);
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);
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| Line 99... |
Line 90... |
reg mode_update_q;
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reg mode_update_q;
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reg [1:0] xcvrselect_q;
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reg [1:0] xcvrselect_q;
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reg termselect_q;
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reg termselect_q;
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reg [1:0] opmode_q;
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reg [1:0] opmode_q;
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reg phy_reset_q;
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reg phy_reset_q;
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reg auto_wr_q;
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reg reg_wr_q;
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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if (ulpi_rst_i)
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begin
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begin
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mode_update_q <= 1'b0;
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mode_update_q <= 1'b0;
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| Line 115... |
Line 104... |
end
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end
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else
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else
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begin
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begin
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xcvrselect_q <= utmi_xcvrselect_i;
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xcvrselect_q <= utmi_xcvrselect_i;
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termselect_q <= utmi_termselect_i;
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termselect_q <= utmi_termselect_i;
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opmode_q <= utmi_opmode_i;
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opmode_q <= utmi_op_mode_i;
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|
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if (mode_update_q && (state_q == STATE_CMD) && (ulpi_data_o == REG_FUNC_CTRL))
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if (mode_update_q && (state_q == STATE_CMD) && (ulpi_data_in_o == REG_FUNC_CTRL))
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begin
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begin
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mode_update_q <= 1'b0;
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mode_update_q <= 1'b0;
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phy_reset_q <= 1'b0;
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phy_reset_q <= 1'b0;
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end
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end
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else if (opmode_q != utmi_opmode_i ||
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else if (opmode_q != utmi_op_mode_i ||
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termselect_q != utmi_termselect_i ||
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termselect_q != utmi_termselect_i ||
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xcvrselect_q != utmi_xcvrselect_i)
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xcvrselect_q != utmi_xcvrselect_i)
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mode_update_q <= 1'b1;
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mode_update_q <= 1'b1;
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end
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end
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| Line 147... |
Line 136... |
else
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else
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begin
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begin
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dppulldown_q <= utmi_dppulldown_i;
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dppulldown_q <= utmi_dppulldown_i;
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dmpulldown_q <= utmi_dmpulldown_i;
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dmpulldown_q <= utmi_dmpulldown_i;
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if (otg_update_q && (state_q == STATE_CMD) && (ulpi_data_o == REG_OTG_CTRL))
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if (otg_update_q && (state_q == STATE_CMD) && (ulpi_data_in_o == REG_OTG_CTRL))
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otg_update_q <= 1'b0;
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otg_update_q <= 1'b0;
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else if (dppulldown_q != utmi_dppulldown_i ||
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else if (dppulldown_q != utmi_dppulldown_i ||
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dmpulldown_q != utmi_dmpulldown_i)
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dmpulldown_q != utmi_dmpulldown_i)
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otg_update_q <= 1'b1;
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otg_update_q <= 1'b1;
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end
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end
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| Line 167... |
Line 156... |
else
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else
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ulpi_dir_q <= ulpi_dir_i;
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ulpi_dir_q <= ulpi_dir_i;
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wire turnaround_w = ulpi_dir_q ^ ulpi_dir_i;
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wire turnaround_w = ulpi_dir_q ^ ulpi_dir_i;
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reg ulpi_rxcmd_q;
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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ulpi_rxcmd_q <= 1'b0;
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// Switch to input with NXT asserted in turnaround cycle
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else if (!ulpi_dir_q && ulpi_dir_i && ulpi_nxt_i)
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ulpi_rxcmd_q <= 1'b1;
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// Switch to output (turnaround cycle)
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else if (ulpi_dir_q && !ulpi_dir_i)
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ulpi_rxcmd_q <= 1'b0;
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//-----------------------------------------------------------------
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// Register Access
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//-----------------------------------------------------------------
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reg reg_wr_pending_q;
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reg reg_rd_pending_q;
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reg [7:0] reg_addr_q;
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reg [7:0] reg_data_q;
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reg reg_ack_q;
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wire reg_ready_w = (reg_wr_pending_q && state_q == STATE_REG && ulpi_nxt_i && reg_wr_q) ||
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(reg_rd_pending_q && !turnaround_w && ulpi_dir_i && !ulpi_rxcmd_q);
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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begin
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reg_wr_pending_q <= 1'b0;
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reg_rd_pending_q <= 1'b0;
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reg_addr_q <= 8'b0;
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end
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else if (reg_stb_i)
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begin
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reg_addr_q <= reg_addr_i;
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reg_wr_pending_q <= reg_we_i;
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reg_rd_pending_q <= ~reg_we_i;
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end
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else if (reg_ready_w)
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begin
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reg_wr_pending_q <= 1'b0;
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reg_rd_pending_q <= 1'b0;
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end
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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reg_data_q <= 8'b0;
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else if (reg_stb_i && reg_we_i)
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reg_data_q <= reg_data_i;
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assign reg_data_o = utmi_data_o;
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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reg_ack_q <= 1'b0;
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else
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reg_ack_q <= reg_ready_w;
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assign reg_ack_o = reg_ack_q;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Rx - Tx delay
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// Rx - Tx delay
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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localparam TX_DELAY_W = 3;
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localparam TX_DELAY_W = 3;
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localparam TX_START_DELAY = 3'd7;
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localparam TX_START_DELAY = 3'd7;
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| Line 269... |
Line 200... |
else
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else
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begin
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begin
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// Push
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// Push
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if (utmi_txvalid_i && utmi_txready_o)
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if (utmi_txvalid_i && utmi_txready_o)
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begin
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begin
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tx_buffer_q[tx_wr_idx_q] <= utmi_data_i;
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tx_buffer_q[tx_wr_idx_q] <= utmi_data_out_i;
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tx_valid_q[tx_wr_idx_q] <= 1'b1;
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tx_valid_q[tx_wr_idx_q] <= 1'b1;
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tx_wr_idx_q <= tx_wr_idx_q + 1'b1;
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tx_wr_idx_q <= tx_wr_idx_q + 1'b1;
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end
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end
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| Line 309... |
Line 240... |
reg utmi_rxactive_q;
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reg utmi_rxactive_q;
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reg [1:0] utmi_linestate_q;
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reg [1:0] utmi_linestate_q;
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reg [7:0] utmi_data_q;
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reg [7:0] utmi_data_q;
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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begin
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if (ulpi_rst_i)
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if (ulpi_rst_i)
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begin
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begin
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state_q <= STATE_IDLE;
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state_q <= STATE_IDLE;
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ulpi_data_q <= 8'b0;
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ulpi_data_q <= 8'b0;
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data_q <= 8'b0;
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data_q <= 8'b0;
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ulpi_stp_q <= 1'b0;
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ulpi_stp_q <= 1'b1;
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utmi_rxvalid_q <= 1'b0;
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utmi_rxvalid_q <= 1'b0;
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utmi_rxerror_q <= 1'b0;
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utmi_rxerror_q <= 1'b0;
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utmi_rxactive_q <= 1'b0;
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utmi_rxactive_q <= 1'b0;
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utmi_linestate_q <= 2'b0;
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utmi_linestate_q <= 2'b0;
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utmi_data_q <= 8'b0;
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utmi_data_q <= 8'b0;
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auto_wr_q <= 1'b0;
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reg_wr_q <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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ulpi_stp_q <= 1'b0;
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ulpi_stp_q <= 1'b0;
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utmi_rxvalid_q <= 1'b0;
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utmi_rxvalid_q <= 1'b0;
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if (!turnaround_w)
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// Turnaround: Input + NXT - set RX_ACTIVE
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if (turnaround_w && ulpi_dir_i && ulpi_nxt_i)
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begin
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utmi_rxactive_q <= 1'b1;
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end
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// Turnaround: Input -> Output - reset RX_ACTIVE
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else if (turnaround_w && !ulpi_dir_i)
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begin
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utmi_rxactive_q <= 1'b0;
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end
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// Non-turnaround cycle
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else if (!turnaround_w)
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begin
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begin
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Input: RX_DATA
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// Input: RX_CMD (status)
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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if (ulpi_dir_i && ulpi_rxcmd_q)
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if (ulpi_dir_i && !ulpi_nxt_i)
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begin
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begin
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utmi_rxvalid_q <= ulpi_nxt_i;
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// Phy status
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utmi_data_q <= ulpi_data_i;
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utmi_linestate_q <= ulpi_data_out_i[1:0];
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|
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// No valid data, extract phy status
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case (ulpi_data_out_i[5:4])
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if (!ulpi_nxt_i)
|
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begin
|
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utmi_linestate_q <= ulpi_data_i[1:0];
|
|
|
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case (ulpi_data_i[5:4])
|
|
2'b00:
|
2'b00:
|
begin
|
begin
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utmi_rxactive_q <= 1'b0;
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utmi_rxactive_q <= 1'b0;
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utmi_rxerror_q <= 1'b0;
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utmi_rxerror_q <= 1'b0;
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end
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end
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| Line 365... |
Line 299... |
end
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end
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default:
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default:
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; // HOST_DISCONNECTED
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; // HOST_DISCONNECTED
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endcase
|
endcase
|
end
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end
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// RxValid (so force RxActive)
|
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else
|
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utmi_rxactive_q <= 1'b1;
|
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end
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Input: REG_DATA
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// Input: RX_DATA
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
else if (ulpi_dir_i)
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else if (ulpi_dir_i && ulpi_nxt_i)
|
begin
|
begin
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utmi_rxvalid_q <= 1'b0;
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utmi_rxvalid_q <= 1'b1;
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utmi_data_q <= ulpi_data_i;
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utmi_data_q <= ulpi_data_out_i;
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end
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end
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Output
|
// Output
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
else
|
else if (!ulpi_dir_i)
|
begin
|
begin
|
// IDLE: Pending mode update
|
// IDLE: Pending mode update
|
if ((state_q == STATE_IDLE) && mode_update_q)
|
if ((state_q == STATE_IDLE) && mode_update_q)
|
begin
|
begin
|
data_q <= {1'b0, 1'b1, phy_reset_q, opmode_q, termselect_q, xcvrselect_q};
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data_q <= {1'b0, 1'b1, phy_reset_q, opmode_q, termselect_q, xcvrselect_q};
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ulpi_data_q <= REG_FUNC_CTRL;
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ulpi_data_q <= REG_FUNC_CTRL;
|
|
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state_q <= STATE_CMD;
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state_q <= STATE_CMD;
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auto_wr_q <= 1'b1;
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reg_wr_q <= 1'b0;
|
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end
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end
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// IDLE: Pending OTG control update
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// IDLE: Pending OTG control update
|
else if ((state_q == STATE_IDLE) && otg_update_q)
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else if ((state_q == STATE_IDLE) && otg_update_q)
|
begin
|
begin
|
data_q <= {5'b0, dmpulldown_q, dppulldown_q, 1'b0};
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data_q <= {5'b0, dmpulldown_q, dppulldown_q, 1'b0};
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ulpi_data_q <= REG_OTG_CTRL;
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ulpi_data_q <= REG_OTG_CTRL;
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|
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state_q <= STATE_CMD;
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state_q <= STATE_CMD;
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auto_wr_q <= 1'b1;
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reg_wr_q <= 1'b0;
|
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end
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// IDLE: Pending register access
|
|
else if ((state_q == STATE_IDLE) && (reg_wr_pending_q || reg_rd_pending_q))
|
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begin
|
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data_q <= reg_data_q;
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|
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if (reg_wr_pending_q)
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ulpi_data_q <= REG_WRITE | {2'b0, reg_addr_q[5:0]};
|
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else
|
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ulpi_data_q <= REG_READ | {2'b0, reg_addr_q[5:0]};
|
|
|
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state_q <= STATE_CMD;
|
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auto_wr_q <= 1'b0;
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reg_wr_q <= reg_wr_pending_q;
|
|
end
|
end
|
// IDLE: Pending transmit
|
// IDLE: Pending transmit
|
else if ((state_q == STATE_IDLE) && utmi_tx_ready_w)
|
else if ((state_q == STATE_IDLE) && utmi_tx_ready_w)
|
begin
|
begin
|
ulpi_data_q <= REG_TRANSMIT | {4'b0, utmi_tx_data_w[3:0]};
|
ulpi_data_q <= REG_TRANSMIT | {4'b0, utmi_tx_data_w[3:0]};
|
state_q <= STATE_DATA;
|
state_q <= STATE_DATA;
|
auto_wr_q <= 1'b0;
|
|
reg_wr_q <= 1'b0;
|
|
end
|
end
|
// Command
|
// Command
|
else if ((state_q == STATE_CMD) && ulpi_nxt_i)
|
else if ((state_q == STATE_CMD) && ulpi_nxt_i)
|
begin
|
begin
|
// Read Register
|
|
if (!reg_wr_q && !auto_wr_q)
|
|
begin
|
|
state_q <= STATE_IDLE;
|
|
ulpi_data_q <= 8'b0;
|
|
end
|
|
// Write Register
|
// Write Register
|
else
|
|
begin
|
|
state_q <= STATE_REG;
|
state_q <= STATE_REG;
|
ulpi_data_q <= data_q;
|
ulpi_data_q <= data_q;
|
end
|
end
|
end
|
|
// Data (register write)
|
// Data (register write)
|
else if (state_q == STATE_REG && ulpi_nxt_i)
|
else if (state_q == STATE_REG && ulpi_nxt_i)
|
begin
|
begin
|
state_q <= STATE_IDLE;
|
state_q <= STATE_IDLE;
|
ulpi_data_q <= 8'b0; // IDLE
|
ulpi_data_q <= 8'b0; // IDLE
|
ulpi_stp_q <= 1'b1;
|
ulpi_stp_q <= 1'b1;
|
auto_wr_q <= 1'b0;
|
|
reg_wr_q <= 1'b0;
|
|
end
|
end
|
// Data
|
// Data
|
else if (state_q == STATE_DATA && ulpi_nxt_i)
|
else if (state_q == STATE_DATA && ulpi_nxt_i)
|
begin
|
begin
|
// End of packet
|
// End of packet
|
| Line 468... |
Line 367... |
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
// Accept from buffer
|
// Accept from buffer
|
assign utmi_tx_accept_w = ((state_q == STATE_IDLE) && !(mode_update_q || otg_update_q || turnaround_w || reg_wr_pending_q || reg_rd_pending_q) && !ulpi_dir_i) ||
|
assign utmi_tx_accept_w = ((state_q == STATE_IDLE) && !(mode_update_q || otg_update_q || turnaround_w) && !ulpi_dir_i) ||
|
(state_q == STATE_DATA && ulpi_nxt_i && !ulpi_dir_i);
|
(state_q == STATE_DATA && ulpi_nxt_i && !ulpi_dir_i);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Assignments
|
// Assignments
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// ULPI Interface
|
// ULPI Interface
|
assign ulpi_data_o = ulpi_data_q;
|
assign ulpi_data_in_o = ulpi_data_q;
|
assign ulpi_stp_o = ulpi_stp_q;
|
assign ulpi_stp_o = ulpi_stp_q;
|
|
|
// UTMI Interface
|
// UTMI Interface
|
assign utmi_linestate_o = utmi_linestate_q;
|
assign utmi_linestate_o = utmi_linestate_q;
|
assign utmi_data_o = utmi_data_q;
|
assign utmi_data_in_o = utmi_data_q;
|
assign utmi_rxerror_o = utmi_rxerror_q;
|
assign utmi_rxerror_o = utmi_rxerror_q;
|
assign utmi_rxactive_o = utmi_rxactive_q;
|
assign utmi_rxactive_o = utmi_rxactive_q;
|
assign utmi_rxvalid_o = utmi_rxvalid_q;
|
assign utmi_rxvalid_o = utmi_rxvalid_q;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
