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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// ULPI (Link) Wrapper
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// ULPI (Link) Wrapper
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// V1.0
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// V1.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2015-2018
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// Copyright 2015-2018
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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Line 90... |
reg mode_update_q;
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reg mode_update_q;
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reg [1:0] xcvrselect_q;
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reg [1:0] xcvrselect_q;
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reg termselect_q;
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reg termselect_q;
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reg [1:0] opmode_q;
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reg [1:0] opmode_q;
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reg phy_reset_q;
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reg phy_reset_q;
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reg mode_write_q;
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// Detect register write completion
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wire mode_complete_w = (state_q == STATE_REG &&
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mode_write_q &&
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ulpi_nxt_i &&
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!ulpi_dir_i); // Not interrupted by a Rx
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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if (ulpi_rst_i)
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begin
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begin
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mode_update_q <= 1'b0;
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mode_update_q <= 1'b0;
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Line 113... |
begin
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begin
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xcvrselect_q <= utmi_xcvrselect_i;
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xcvrselect_q <= utmi_xcvrselect_i;
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termselect_q <= utmi_termselect_i;
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termselect_q <= utmi_termselect_i;
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opmode_q <= utmi_op_mode_i;
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opmode_q <= utmi_op_mode_i;
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if (mode_update_q && (state_q == STATE_CMD) && (ulpi_data_in_o == REG_FUNC_CTRL))
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if (mode_update_q && mode_complete_w)
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begin
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begin
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mode_update_q <= 1'b0;
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mode_update_q <= 1'b0;
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phy_reset_q <= 1'b0;
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phy_reset_q <= 1'b0;
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end
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end
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else if (opmode_q != utmi_op_mode_i ||
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else if (opmode_q != utmi_op_mode_i ||
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// UTMI OTG Control
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// UTMI OTG Control
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg otg_update_q;
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reg otg_update_q;
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reg dppulldown_q;
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reg dppulldown_q;
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reg dmpulldown_q;
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reg dmpulldown_q;
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reg otg_write_q;
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// Detect register write completion
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wire otg_complete_w = (state_q == STATE_REG &&
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otg_write_q &&
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ulpi_nxt_i &&
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!ulpi_dir_i); // Not interrupted by a Rx
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
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if (ulpi_rst_i)
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if (ulpi_rst_i)
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begin
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begin
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otg_update_q <= 1'b0;
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otg_update_q <= 1'b0;
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else
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else
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begin
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begin
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dppulldown_q <= utmi_dppulldown_i;
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dppulldown_q <= utmi_dppulldown_i;
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dmpulldown_q <= utmi_dmpulldown_i;
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dmpulldown_q <= utmi_dmpulldown_i;
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if (otg_update_q && (state_q == STATE_CMD) && (ulpi_data_in_o == REG_OTG_CTRL))
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if (otg_update_q && otg_complete_w)
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otg_update_q <= 1'b0;
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otg_update_q <= 1'b0;
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else if (dppulldown_q != utmi_dppulldown_i ||
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else if (dppulldown_q != utmi_dppulldown_i ||
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dmpulldown_q != utmi_dmpulldown_i)
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dmpulldown_q != utmi_dmpulldown_i)
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otg_update_q <= 1'b1;
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otg_update_q <= 1'b1;
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end
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end
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utmi_rxvalid_q <= 1'b0;
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utmi_rxvalid_q <= 1'b0;
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utmi_rxerror_q <= 1'b0;
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utmi_rxerror_q <= 1'b0;
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utmi_rxactive_q <= 1'b0;
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utmi_rxactive_q <= 1'b0;
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utmi_linestate_q <= 2'b0;
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utmi_linestate_q <= 2'b0;
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utmi_data_q <= 8'b0;
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utmi_data_q <= 8'b0;
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mode_write_q <= 1'b0;
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otg_write_q <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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ulpi_stp_q <= 1'b0;
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ulpi_stp_q <= 1'b0;
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utmi_rxvalid_q <= 1'b0;
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utmi_rxvalid_q <= 1'b0;
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// Turnaround: Input + NXT - set RX_ACTIVE
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// Turnaround: Input + NXT - set RX_ACTIVE
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if (turnaround_w && ulpi_dir_i && ulpi_nxt_i)
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if (turnaround_w && ulpi_dir_i && ulpi_nxt_i)
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begin
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begin
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utmi_rxactive_q <= 1'b1;
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utmi_rxactive_q <= 1'b1;
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// Register write - abort
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if (state_q == STATE_REG)
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begin
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state_q <= STATE_IDLE;
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ulpi_data_q <= 8'b0; // IDLE
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end
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end
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end
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// Turnaround: Input -> Output - reset RX_ACTIVE
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// Turnaround: Input -> Output - reset RX_ACTIVE
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else if (turnaround_w && !ulpi_dir_i)
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else if (turnaround_w && !ulpi_dir_i)
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begin
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begin
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utmi_rxactive_q <= 1'b0;
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utmi_rxactive_q <= 1'b0;
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// Register write - abort
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if (state_q == STATE_REG)
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begin
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state_q <= STATE_IDLE;
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ulpi_data_q <= 8'b0; // IDLE
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end
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end
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end
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// Non-turnaround cycle
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// Non-turnaround cycle
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else if (!turnaround_w)
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else if (!turnaround_w)
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begin
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begin
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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Line 349... |
if ((state_q == STATE_IDLE) && mode_update_q)
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if ((state_q == STATE_IDLE) && mode_update_q)
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begin
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begin
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data_q <= {1'b0, 1'b1, phy_reset_q, opmode_q, termselect_q, xcvrselect_q};
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data_q <= {1'b0, 1'b1, phy_reset_q, opmode_q, termselect_q, xcvrselect_q};
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ulpi_data_q <= REG_FUNC_CTRL;
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ulpi_data_q <= REG_FUNC_CTRL;
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otg_write_q <= 1'b0;
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mode_write_q <= 1'b1;
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state_q <= STATE_CMD;
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state_q <= STATE_CMD;
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end
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end
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// IDLE: Pending OTG control update
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// IDLE: Pending OTG control update
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else if ((state_q == STATE_IDLE) && otg_update_q)
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else if ((state_q == STATE_IDLE) && otg_update_q)
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begin
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begin
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data_q <= {5'b0, dmpulldown_q, dppulldown_q, 1'b0};
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data_q <= {5'b0, dmpulldown_q, dppulldown_q, 1'b0};
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ulpi_data_q <= REG_OTG_CTRL;
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ulpi_data_q <= REG_OTG_CTRL;
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otg_write_q <= 1'b1;
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mode_write_q <= 1'b0;
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state_q <= STATE_CMD;
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state_q <= STATE_CMD;
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end
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end
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// IDLE: Pending transmit
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// IDLE: Pending transmit
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else if ((state_q == STATE_IDLE) && utmi_tx_ready_w)
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else if ((state_q == STATE_IDLE) && utmi_tx_ready_w)
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begin
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begin
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Line 384... |
else if (state_q == STATE_REG && ulpi_nxt_i)
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else if (state_q == STATE_REG && ulpi_nxt_i)
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begin
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begin
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state_q <= STATE_IDLE;
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state_q <= STATE_IDLE;
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ulpi_data_q <= 8'b0; // IDLE
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ulpi_data_q <= 8'b0; // IDLE
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ulpi_stp_q <= 1'b1;
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ulpi_stp_q <= 1'b1;
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otg_write_q <= 1'b0;
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mode_write_q <= 1'b0;
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end
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end
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// Data
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// Data
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else if (state_q == STATE_DATA && ulpi_nxt_i)
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else if (state_q == STATE_DATA && ulpi_nxt_i)
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begin
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begin
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// End of packet
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// End of packet
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Line 429... |
assign utmi_rxvalid_o = utmi_rxvalid_q;
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assign utmi_rxvalid_o = utmi_rxvalid_q;
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endmodule
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endmodule
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