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Line 38... |
-- // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // --
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-- // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // --
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-- // POSSIBILITY OF SUCH DAMAGE. // --
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-- // POSSIBILITY OF SUCH DAMAGE. // --
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-- // // --
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-- // // --
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-- /////////////////////////////////////////////////////////////////// --
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-- /////////////////////////////////////////////////////////////////// --
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--======================================================================================--
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--======================================================================================--
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-- --
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-- Change history --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- | Vers. | Date | Autor | Comment | --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- | 1.0 |04 Feb 2011| MN | Initial version | --
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-- | 1.1 |23 Apr 2011| MN | Added 'rst' to most latched signals. | --
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-- | | | | Added ELSE construct in fs_next_state process to | --
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-- | | | | prevent an undesired latch implementation. | --
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--======================================================================================--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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| Line 121... |
Line 131... |
if rising_edge(clk) then
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if rising_edge(clk) then
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rx_en <= RxEn_i;
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rx_en <= RxEn_i;
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end if;
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end if;
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end process;
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end process;
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p_sync_err: process (clk)
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p_sync_err: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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sync_err <= '0';
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elsif rising_edge(clk) then
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sync_err <= not rx_active and sync_err_d;
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sync_err <= not rx_active and sync_err_d;
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end if;
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end if;
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end process;
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end process;
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--====================================================================================--
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--====================================================================================--
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| Line 174... |
Line 186... |
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j <= rxdp_s and not rxdn_s;
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j <= rxdp_s and not rxdn_s;
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k <= not rxdp_s and rxdn_s;
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k <= not rxdp_s and rxdn_s;
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se0 <= not rxdp_s and not rxdn_s;
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se0 <= not rxdp_s and not rxdn_s;
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p_se0_s: process (clk)
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p_se0_s: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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se0_s <= '0';
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elsif rising_edge(clk) then
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if fs_ce ='1' then
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if fs_ce ='1' then
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se0_s <= se0;
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se0_s <= se0;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 277... |
Line 291... |
if fs_ce='1' and rx_active='0' and se0='0' and se0_s='0' then
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if fs_ce='1' and rx_active='0' and se0='0' and se0_s='0' then
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case fs_state is
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case fs_state is
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when FS_IDLE => if k ='1' and rx_en ='1' then -- 0
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when FS_IDLE => if k ='1' and rx_en ='1' then -- 0
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fs_next_state <= K1;
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fs_next_state <= K1;
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sync_err_d <= '0';
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sync_err_d <= '0';
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else
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fs_next_state <= FS_IDLE;
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sync_err_d <= '0';
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end if;
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end if;
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when K1 => if j ='1' and rx_en ='1' then -- 1
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when K1 => if j ='1' and rx_en ='1' then -- 1
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fs_next_state <= J1;
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fs_next_state <= J1;
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sync_err_d <= '0';
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sync_err_d <= '0';
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else
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else
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| Line 358... |
Line 375... |
rx_active <= '0';
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rx_active <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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p_rx_valid_r: process (clk)
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p_rx_valid_r: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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rx_valid_r <= '0';
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elsif rising_edge(clk) then
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if rx_valid ='1' then
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if rx_valid ='1' then
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rx_valid_r <= '1';
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rx_valid_r <= '1';
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elsif fs_ce ='1' then
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elsif fs_ce ='1' then
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rx_valid_r <= '0';
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rx_valid_r <= '0';
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end if;
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end if;
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| Line 373... |
Line 392... |
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--====================================================================================--
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--====================================================================================--
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-- NRZI Decoder --
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-- NRZI Decoder --
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--====================================================================================--
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--====================================================================================--
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p_sd_r: process (clk)
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p_sd_r: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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sd_r <= '0';
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elsif rising_edge(clk) then
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if fs_ce ='1' then
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if fs_ce ='1' then
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sd_r <= rxd_s;
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sd_r <= rxd_s;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 418... |
Line 439... |
end if;
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end if;
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end process;
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end process;
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drop_bit <= '1' when one_cnt ="110" else '0';
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drop_bit <= '1' when one_cnt ="110" else '0';
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p_bit_stuff_err: process (clk) -- Bit Stuff Error
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p_bit_stuff_err: process (clk, rst) -- Bit Stuff Error
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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bit_stuff_err <= '0';
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elsif rising_edge(clk) then
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bit_stuff_err <= drop_bit and sd_nrzi and fs_ce and not se0 and rx_active;
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bit_stuff_err <= drop_bit and sd_nrzi and fs_ce and not se0 and rx_active;
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end if;
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end if;
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end process;
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end process;
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--====================================================================================--
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--====================================================================================--
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-- Serial => Parallel converter --
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-- Serial => Parallel converter --
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--====================================================================================--
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--====================================================================================--
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p_shift_en: process (clk)
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p_shift_en: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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shift_en <= '0';
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elsif rising_edge(clk) then
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if fs_ce ='1' then
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if fs_ce ='1' then
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shift_en <= synced_d or rx_active;
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shift_en <= synced_d or rx_active;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 477... |
Line 502... |
rx_valid1 <= '0';
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rx_valid1 <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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p_rx_valid: process (clk)
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p_rx_valid: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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rx_valid <= '0';
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elsif rising_edge(clk) then
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rx_valid <= not drop_bit and rx_valid1 and fs_ce;
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rx_valid <= not drop_bit and rx_valid1 and fs_ce;
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end if;
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end if;
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end process;
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end process;
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p_se0_r: process (clk)
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p_se0_r: process (clk)
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| Line 491... |
Line 518... |
if rising_edge(clk) then
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if rising_edge(clk) then
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se0_r <= se0;
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se0_r <= se0;
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end if;
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end if;
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end process;
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end process;
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p_byte_err: process (clk)
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p_byte_err: process (clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rst ='0' then
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byte_err <= '0';
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elsif rising_edge(clk) then
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byte_err <= se0 and not se0_r and (bit_cnt(1) or bit_cnt(2)) and rx_active;
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byte_err <= se0 and not se0_r and (bit_cnt(1) or bit_cnt(2)) and rx_active;
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end if;
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end if;
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end process;
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end process;
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end RTL;
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end RTL;
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