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-- // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // --
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-- // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // --
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-- // POSSIBILITY OF SUCH DAMAGE. // --
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-- // POSSIBILITY OF SUCH DAMAGE. // --
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-- // // --
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-- // // --
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-- /////////////////////////////////////////////////////////////////// --
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-- /////////////////////////////////////////////////////////////////// --
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--======================================================================================--
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--======================================================================================--
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-- --
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-- Change history --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- | Vers. | Date | Autor | Comment | --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- | 1.0 |04 Feb 2011| MN | Initial version | --
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-- | 1.1 |23 Apr 2011| MN | Added missing 'rst' in process sensitivity lists | --
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-- | | | | Added ELSE constructs in next_state process to | --
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-- | | | | prevent an undesired latch implementation. | --
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--======================================================================================--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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Line 221... |
end process;
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end process;
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sft_done_e <= sft_done and not sft_done_r;
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sft_done_e <= sft_done and not sft_done_r;
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-- Out Data Hold Register
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-- Out Data Hold Register
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p_hold_reg: process (clk)
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p_hold_reg: process (clk, rst)
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begin
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begin
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if rst ='0' then
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if rst ='0' then
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hold_reg <= X"00";
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hold_reg <= X"00";
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hold_reg_d <= X"00";
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hold_reg_d <= X"00";
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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Line 398... |
next_state <= IDLE_STATE;
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next_state <= IDLE_STATE;
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else
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else
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case (state) is
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case (state) is
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when IDLE_STATE => if TxValid_i ='1' then
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when IDLE_STATE => if TxValid_i ='1' then
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next_state <= SOP_STATE;
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next_state <= SOP_STATE;
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ELSE
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next_state <= IDLE_STATE;
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end if;
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end if;
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when SOP_STATE => if sft_done_e ='1' then
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when SOP_STATE => if sft_done_e ='1' then
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next_state <= DATA_STATE;
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next_state <= DATA_STATE;
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ELSE
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next_state <= SOP_STATE;
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end if;
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end if;
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when DATA_STATE => if data_done ='0' and sft_done_e ='1' then
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when DATA_STATE => if data_done ='0' and sft_done_e ='1' then
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next_state <= EOP1_STATE;
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next_state <= EOP1_STATE;
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ELSE
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next_state <= DATA_STATE;
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end if;
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end if;
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when EOP1_STATE => if eop_done ='1' then
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when EOP1_STATE => if eop_done ='1' then
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next_state <= EOP2_STATE;
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next_state <= EOP2_STATE;
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ELSE
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next_state <= EOP1_STATE;
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end if;
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end if;
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when EOP2_STATE => if eop_done ='0' and fs_ce ='1' then
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when EOP2_STATE => if eop_done ='0' and fs_ce ='1' then
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next_state <= WAIT_STATE;
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next_state <= WAIT_STATE;
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ELSE
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next_state <= EOP2_STATE;
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end if;
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end if;
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when others => if fs_ce = '1' then --is WAIT_STATE
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when WAIT_STATE => if fs_ce = '1' then
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next_state <= IDLE_STATE;
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next_state <= IDLE_STATE;
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ELSE
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next_state <= WAIT_STATE;
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end if;
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end if;
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when others => next_state <= IDLE_STATE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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ld_sop_d <= TxValid_i when state = IDLE_STATE else '0';
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ld_sop_d <= TxValid_i when state = IDLE_STATE else '0';
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