| Line 5... |
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-- This source file may be used and distributed without restriction provided that this copyright statement --
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-- This source file may be used and distributed without restriction provided that this copyright statement --
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-- is not removed from the file and that any derivative work contains the original copyright notice and --
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-- is not removed from the file and that any derivative work contains the original copyright notice and --
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-- the associated disclaimer. --
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-- the associated disclaimer. --
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-- --
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-- --
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-- This software is provided ''as is'' and without any express or implied warranties, including, but not --
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-- This software is provided ''as is'' and without any express or implied warranties, including, but not --
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-- limited to, the implied warranties of merchantability and fitness for a particular purpose. in no event --
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-- limited to, the implied warranties of merchantability and fitness for a particular purpose. In no event --
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-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
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-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
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-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
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-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
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-- of use, data, or profits; or business interruption) however caused and on any theory of liability, --
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-- of use, data, or profits; or business interruption) however caused and on any theory of liability, --
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-- whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way --
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-- whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way --
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-- out of the use of this software, even if advised of the possibility of such damage. --
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-- out of the use of this software, even if advised of the possibility of such damage. --
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-- Change history --
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-- Change history --
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-- --
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-- --
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-- Version / date Description --
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-- Version / date Description --
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-- --
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-- --
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-- 01 05 Mar 2011 MN Initial version --
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-- 01 05 Mar 2011 MN Initial version --
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-- 02 01 Nov 2011 MN Removed application specific interface, gererate 12 MHz clk internally --
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-- --
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-- --
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-- End change history --
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-- End change history --
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--==========================================================================================================--
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--==========================================================================================================--
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-- --
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-- --
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-- http://en.wikipedia.org/wiki/Universal_Serial_Bus --
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-- http://en.wikipedia.org/wiki/Universal_Serial_Bus --
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LIBRARY work;
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LIBRARY work;
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USE work.usb_commands.all;
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USE work.usb_commands.all;
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ENTITY usb_fs_master IS PORT(
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ENTITY usb_fs_master IS PORT(
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-- USB Interface --
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usb_clk : IN STD_LOGIC;
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int_clk : IN STD_LOGIC;
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rst_neg_ext : OUT STD_LOGIC;
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rst_neg_ext : OUT STD_LOGIC;
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usb_Dp : INOUT STD_LOGIC;
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usb_Dp : INOUT STD_LOGIC;
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usb_Dn : INOUT STD_LOGIC;
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usb_Dn : INOUT STD_LOGIC
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-- Application Interface
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);
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RXval : IN STD_LOGIC; -- RX bytes available
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RXdat : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Received data bytes
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RXrdy : OUT STD_LOGIC := '0'; -- Application ready for data
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RXlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Number of bytes available
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TXval : OUT STD_LOGIC := '0'; -- Application has valid data
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TXdat : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data byte to send
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TXrdy : IN STD_LOGIC; -- Entity is ready for data
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TXroom : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- No of free bytes in TX
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TXcork : OUT STD_LOGIC := '1'); -- Hold TX transmission
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END usb_fs_master;
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END usb_fs_master;
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ARCHITECTURE SIM OF usb_fs_master IS
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ARCHITECTURE SIM OF usb_fs_master IS
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|
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SIGNAL T_No : NATURAL;
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SIGNAL T_No : NATURAL;
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SIGNAL usb_clk : STD_LOGIC;
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SIGNAL crc_16 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL crc_16 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL crc_5 : STD_LOGIC_VECTOR( 4 DOWNTO 0);
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SIGNAL crc_5 : STD_LOGIC_VECTOR( 4 DOWNTO 0);
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SIGNAL master_oe : STD_LOGIC;
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SIGNAL master_oe : STD_LOGIC;
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SIGNAL stimuli_bit : STD_LOGIC := 'Z';
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SIGNAL stimuli_bit : STD_LOGIC := 'Z';
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SIGNAL stop_sim : BOOLEAN := false;
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SIGNAL stuffing_requ : BOOLEAN;
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SIGNAL stuffing_requ : BOOLEAN;
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SIGNAL usb_request : usb_action;
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SIGNAL usb_request : usb_action;
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|
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function next_CRC_5 (Data: std_logic; crc: std_logic_vector(4 downto 0)) return std_logic_vector is
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function next_CRC_5 (Data: std_logic; crc: std_logic_vector(4 downto 0)) return std_logic_vector is
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-- Copyright (C) 1999-2008 Easics NV. http://www.easics.com/webtools/crctool
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-- Copyright (C) 1999-2008 Easics NV. http://www.easics.com/webtools/crctool
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| Line 133... |
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|
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--==========================================================================================================--
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--==========================================================================================================--
|
|
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begin
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begin
|
|
|
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p_usb_clk : PROCESS
|
|
BEGIN
|
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usb_clk <= '0';
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WAIT FOR 20866 ps;
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usb_clk <= '1';
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WAIT FOR 41600 ps;
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usb_clk <= '0';
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WAIT FOR 20867 ps;
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END PROCESS;
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test_case : ENTITY work.usb_stimuli
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test_case : ENTITY work.usb_stimuli
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PORT MAP(
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PORT MAP(
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-- Test Control Interface --
|
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usb => usb_request,
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usb => usb_request,
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T_No => T_No,
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-- Application Interface
|
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clk => int_clk,
|
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rst_neg_ext => rst_neg_ext,
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rst_neg_ext => rst_neg_ext,
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RXval => RXval,
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T_No => T_No
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RXdat => RXdat,
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RXrdy => RXrdy,
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RXlen => RXlen,
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TXval => TXval,
|
|
TXdat => TXdat,
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TXrdy => TXrdy,
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TXroom => TXroom,
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TXcork => TXcork
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);
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);
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usb_fs_monitor : ENTITY work.usb_fs_monitor
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usb_fs_monitor : ENTITY work.usb_fs_monitor
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port map (
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port map (
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clk_60MHz => int_clk,
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master_oe => master_oe,
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master_oe => master_oe,
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usb_Dp => usb_dp,
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usb_Dp => usb_dp,
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usb_Dn => usb_dn
|
usb_Dn => usb_dn
|
);
|
);
|
|
|
