| Line 5... |
Line 5... |
-- --
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-- --
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-- This source file may be used and distributed without restriction provided that this copyright statement --
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-- This source file may be used and distributed without restriction provided that this copyright statement --
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-- is not removed from the file and that any derivative work contains the original copyright notice and --
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-- is not removed from the file and that any derivative work contains the original copyright notice and --
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-- the associated disclaimer. --
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-- the associated disclaimer. --
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-- --
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-- --
|
-- This software is provided ''as is'' and without any express or implied warranties, including, but not --
|
-- This software is provided ''as is'' and without any expressed or implied warranties, including, but not --
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-- limited to, the implied warranties of merchantability and fitness for a particular purpose. in no event --
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-- limited to, the implied warranties of merchantability and fitness for a particular purpose. In no event --
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-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
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-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
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-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
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-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
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-- of use, data, or profits; or business interruption) however caused and on any theory of liability, --
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-- of use, data, or profits; or business interruption) however caused and on any theory of liability, --
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-- whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way --
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-- whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way --
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-- out of the use of this software, even if advised of the possibility of such damage. --
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-- out of the use of this software, even if advised of the possibility of such damage. --
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-- --
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-- --
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--==========================================================================================================--
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--==========================================================================================================--
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-- --
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-- --
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-- File name : USB_tb.vhd --
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-- File name : USB_tb.vhd --
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-- Author : Martin Neumann martin@neumanns-mail.de --
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-- Author : Martin Neumann martin@neumanns-mail.de --
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-- Description : USB test bench used with usb_mster.vhd, usb_Stimuli.vhd and usb_fs_monitor.vhd. --
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-- Description : USB test bench - an example how to use the usb_master files together an US application. --
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-- --
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-- --
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--==========================================================================================================--
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--==========================================================================================================--
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-- --
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-- --
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-- Change history --
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-- Change history --
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-- --
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-- --
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-- Version / date Description --
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-- Version / date Description --
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-- --
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-- --
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-- 01 05 Mar 2011 MN Initial version --
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-- 01 05 Mar 2011 MN Initial version --
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-- 02 15 Apr 2013 MN Simplified --
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-- --
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-- --
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-- End change history --
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-- End change history --
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--==========================================================================================================--
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--==========================================================================================================--
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|
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LIBRARY work, IEEE;
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LIBRARY work, IEEE;
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| Line 39... |
Line 40... |
ENTITY usb_tb IS
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ENTITY usb_tb IS
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END usb_tb;
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END usb_tb;
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ARCHITECTURE sim OF usb_tb IS
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ARCHITECTURE sim OF usb_tb IS
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|
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CONSTANT BUFSIZE_BITS : POSITIVE := 8;
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CONSTANT BUFSIZE_BITS : Integer := 8;
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TYPE outp_mode IS(RECV, SEND);
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SIGNAL FPGA_ready : STD_LOGIC;
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SIGNAL clk_60mhz : STD_LOGIC;
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SIGNAL RXdat : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL fpga_ready : STD_LOGIC;
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SIGNAL RXlen : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0);
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SIGNAL RXrdy : STD_LOGIC;
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SIGNAL RXval : STD_LOGIC;
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SIGNAL TXcork : STD_LOGIC;
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SIGNAL TXdat : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL TXrdy : STD_LOGIC;
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SIGNAL TXroom : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0);
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SIGNAL TXval : STD_LOGIC;
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SIGNAL USB_rst : STD_LOGIC;
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SIGNAL online : STD_LOGIC;
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SIGNAL online : STD_LOGIC;
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SIGNAL clk_12MHz : STD_LOGIC;
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SIGNAL outp_cntl : outp_mode;
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SIGNAL clk_60MHz : STD_LOGIC;
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SIGNAL outp_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL rst_neg_ext : STD_LOGIC;
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SIGNAL rst_neg_ext : STD_LOGIC;
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SIGNAL rst_neg_syc : STD_LOGIC;
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SIGNAL reset_sync : STD_LOGIC;
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SIGNAL usb_Dn : STD_LOGIC := 'L';
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SIGNAL rxdat : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL usb_Dp : STD_LOGIC := 'Z'; -- allow forcing 'H', avoid 'X'
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SIGNAL rxlen : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0);
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SIGNAL rxrdy : STD_LOGIC;
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SIGNAL rxval : STD_LOGIC;
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SIGNAL txcork : STD_LOGIC;
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SIGNAL txdat : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL txrdy : STD_LOGIC;
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SIGNAL txroom : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0);
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SIGNAL txval : STD_LOGIC;
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SIGNAL usb_dn : STD_LOGIC := 'L';
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SIGNAL usb_dp : STD_LOGIC := 'Z'; -- allow forcing 'H', avoid 'X'
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SIGNAL usb_rst : STD_LOGIC;
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|
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BEGIN
|
BEGIN
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|
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p_clk_60MHz : PROCESS
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p_clk_60MHz : PROCESS
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BEGIN
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BEGIN
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| Line 70... |
Line 72... |
WAIT FOR 2 ns;
|
WAIT FOR 2 ns;
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While true loop
|
While true loop
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clk_60MHz <= '0';
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clk_60MHz <= '0';
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WAIT FOR 8000 ps;
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WAIT FOR 8000 ps;
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clk_60MHz <= '1';
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clk_60MHz <= '1';
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-- WAIT FOR 8667 ps; -- 60 MHz
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WAIT FOR 8667 ps; -- 60 MHz
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WAIT FOR 8393 ps; -- 61 MHz
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-- WAIT FOR 8393 ps; -- 61 MHz
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-- WAIT FOR 8949 ps; -- 59 MHz
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-- WAIT FOR 8949 ps; -- 59 MHz
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end loop;
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end loop;
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END PROCESS;
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END PROCESS;
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p_clk_12MHz : PROCESS
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BEGIN
|
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clk_12MHz <= '0';
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WAIT FOR 20866 ps;
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clk_12MHz <= '1';
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WAIT FOR 41600 ps;
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clk_12MHz <= '0';
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WAIT FOR 20867 ps;
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END PROCESS;
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p_rst_neg_ext : PROCESS
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BEGIN
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rst_neg_ext <= '0';
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WAIT FOR 301 ns;
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rst_neg_ext <= '1';
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WAIT;
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END PROCESS;
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usb_fs_master : ENTITY work.usb_fs_master
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usb_fs_master : ENTITY work.usb_fs_master
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port map (
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PORT MAP (
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usb_clk => clk_12MHz,
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int_clk => clk_60MHz,
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rst_neg_ext => rst_neg_ext,
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rst_neg_ext => rst_neg_ext,
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usb_Dp => usb_dp,
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usb_Dp => usb_dp,
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usb_Dn => usb_dn,
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usb_Dn => usb_dn
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RXval => RXval,
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RXdat => RXdat,
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RXrdy => RXrdy,
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RXlen => RXlen,
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TXval => TXval,
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TXdat => TXdat,
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TXrdy => TXrdy,
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TXroom => TXroom,
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TXcork => TXcork
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|
);
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);
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|
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usb_dp <= 'H' WHEN FPGA_ready ='1' ELSE 'L'; -- connect FPGA_ready to the pullup resistor logic, ....
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usb_dp <= 'L' WHEN reset_sync ='1' OR FPGA_ready ='0' ELSE 'H' after 10 ns;
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usb_dn <= 'L'; -- ... keeping usb_dp='L' during FPGA initialization.
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usb_dn <= 'L';
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usb_fs_slave_1 : ENTITY work.usb_fs_slave
|
usb_fs_slave_1 : ENTITY work.usb_fs_port
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GENERIC MAP(
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GENERIC MAP(
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VENDORID => X"FB9A",
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VENDORID => X"FB9A",
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PRODUCTID => X"FB9A",
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PRODUCTID => X"FB9A",
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VERSIONBCD => X"0020",
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VERSIONBCD => X"0020",
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SELFPOWERED => FALSE,
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SELFPOWERED => FALSE,
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BUFSIZE_BITS => BUFSIZE_BITS)
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BUFSIZE_BITS => BUFSIZE_BITS)
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PORT MAP(
|
PORT MAP(
|
clk => clk_60MHz, -- i
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clk => clk_60MHz, -- i
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rst_neg_ext => rst_neg_ext, -- i
|
rst_neg_ext => rst_neg_ext, -- i
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rst_neg_syc => rst_neg_syc, -- o RST_NEG_EXT streched to next clock
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reset_syc => reset_sync, -- o positive active, streched to the next clock
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d_pos => usb_dp, -- io Pos USB data line
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d_pos => usb_dp, -- io Pos USB data line
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d_neg => usb_dn, -- io Neg USB data line
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d_neg => usb_dn, -- io Neg USB data line
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d_oe => OPEN,
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USB_rst => USB_rst, -- o USB reset detected (SE0 > 2.5 us)
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USB_rst => USB_rst, -- o USB reset detected (SE0 > 2.5 us)
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online => online, -- o High when the device is in Config state.
|
online => online, -- o High when the device is in Config state.
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RXval => RXval, -- o High if a received byte available on RXDAT.
|
RXval => RXval, -- o High if a received byte available on RXDAT.
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RXdat => RXdat, -- o Received data byte, valid if RXVAL is high.
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RXdat => RXdat, -- o Received data byte, valid if RXVAL is high.
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RXrdy => RXrdy, -- i High if application is ready to receive.
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RXrdy => RXrdy, -- i High if application is ready to receive.
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| Line 142... |
Line 116... |
TXroom => TXroom, -- o No of free bytes in transmit buffer.
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TXroom => TXroom, -- o No of free bytes in transmit buffer.
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TXcork => TXcork, -- i Temp. suppress transmissions at the outgoing endpoint.
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TXcork => TXcork, -- i Temp. suppress transmissions at the outgoing endpoint.
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FPGA_ready => FPGA_ready -- o Connect FPGA_ready to the pullup resistor logic
|
FPGA_ready => FPGA_ready -- o Connect FPGA_ready to the pullup resistor logic
|
);
|
);
|
|
|
|
TXcork <= '0'; -- Don't hold TX transmission
|
|
TXdat <= outp_reg;
|
|
|
|
simple_application : process (clk_60MHz, reset_sync)
|
|
-- returns received bytes with twisted high - and low order nibbles --
|
|
begin
|
|
if reset_sync ='1' then
|
|
outp_cntl <= RECV;
|
|
outp_reg <= (OTHERS => '0');
|
|
TXval <= '0';
|
|
RXrdy <= '0';
|
|
elsif rising_edge(clk_60MHz) then
|
|
if outp_cntl = RECV then
|
|
TXval <= '0';
|
|
if RXval = '1' then
|
|
RXrdy <= '0';
|
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outp_reg <= RXdat(3 DOWNTO 0) & RXdat(7 DOWNTO 4);
|
|
outp_cntl <= SEND;
|
|
else
|
|
-- RXrdy <= online;
|
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RXrdy <= '1';
|
|
outp_cntl <= RECV;
|
|
end if;
|
|
else -- outp_cntl = SEND
|
|
if TXrdy = '1' then
|
|
TXval <= '1';
|
|
RXrdy <= '1';
|
|
outp_cntl <= RECV;
|
|
else
|
|
TXval <= '0';
|
|
RXrdy <= '0';
|
|
outp_cntl <= SEND;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
END sim;
|
END sim;
|
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No newline at end of file
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No newline at end of file
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