| Line 5... |
Line 5... |
-- This source file may be used and distributed without restriction provided that this copyright statement --
|
-- This source file may be used and distributed without restriction provided that this copyright statement --
|
-- is not removed from the file and that any derivative work contains the original copyright notice and --
|
-- is not removed from the file and that any derivative work contains the original copyright notice and --
|
-- the associated disclaimer. --
|
-- the associated disclaimer. --
|
-- --
|
-- --
|
-- This software is provided ''as is'' and without any express or implied warranties, including, but not --
|
-- This software is provided ''as is'' and without any express or implied warranties, including, but not --
|
-- limited to, the implied warranties of merchantability and fitness for a particular purpose. in no event --
|
-- limited to, the implied warranties of merchantability and fitness for a particular purpose. In no event --
|
-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
|
-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
|
-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
|
-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
|
-- of use, data, or profits; or business interruption) however caused and on any theory of liability, --
|
-- of use, data, or profits; or business interruption) however caused and on any theory of liability, --
|
-- whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way --
|
-- whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way --
|
-- out of the use of this software, even if advised of the possibility of such damage. --
|
-- out of the use of this software, even if advised of the possibility of such damage. --
|
| Line 25... |
Line 25... |
-- Change history --
|
-- Change history --
|
-- --
|
-- --
|
-- Version / date Description --
|
-- Version / date Description --
|
-- --
|
-- --
|
-- 01 05 Mar 2011 MN Initial version --
|
-- 01 05 Mar 2011 MN Initial version --
|
|
-- 02 01 Nov 2011 MN clk_60MHz now internally generated; next_state corrected --
|
|
-- 03 30 Jan 2012 MN fixed problems at transfer end, modified for protocol checking --
|
-- --
|
-- --
|
-- End change history --
|
-- End change history --
|
--==========================================================================================================--
|
--==========================================================================================================--
|
|
|
LIBRARY IEEE;
|
LIBRARY work, IEEE;
|
|
USE work.usb_commands.ALL;
|
USE IEEE.std_logic_1164.all;
|
USE IEEE.std_logic_1164.all;
|
USE IEEE.std_logic_textio.all;
|
USE IEEE.std_logic_textio.all;
|
USE std.textio.all;
|
USE std.textio.all;
|
LIBRARY work;
|
|
USE work.usb_commands.all;
|
|
|
|
ENTITY usb_fs_monitor IS PORT(
|
ENTITY usb_fs_monitor IS PORT(
|
clk_60MHz : IN STD_LOGIC;
|
|
master_oe : IN STD_LOGIC;
|
master_oe : IN STD_LOGIC;
|
usb_Dp : IN STD_LOGIC;
|
usb_Dp : IN STD_LOGIC;
|
usb_Dn : IN STD_LOGIC);
|
usb_Dn : IN STD_LOGIC);
|
END usb_fs_monitor;
|
END usb_fs_monitor;
|
|
|
ARCHITECTURE SIM OF usb_fs_monitor IS
|
ARCHITECTURE SIM OF usb_fs_monitor IS
|
TYPE state_mode IS(idle, pid, addr, frame, data, spec, eop);
|
TYPE state_mode IS(idle, pid, token1, token2, frame1, frame2, data, eop, err);
|
|
SIGNAL clk_en : STD_LOGIC;
|
|
SIGNAL clk_60MHz : STD_LOGIC;
|
SIGNAL usb_state : state_mode;
|
SIGNAL usb_state : state_mode;
|
|
SIGNAL byte_valid : STD_LOGIC;
|
SIGNAL usb_dp_sync : STD_LOGIC;
|
SIGNAL usb_dp_sync : STD_LOGIC;
|
SIGNAL usb_dn_sync : STD_LOGIC;
|
SIGNAL usb_dn_sync : STD_LOGIC;
|
SIGNAL clk_en : STD_LOGIC;
|
SIGNAL usb_bit : STD_LOGIC;
|
SIGNAL usb_byte : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
SIGNAL usb_byte : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
SIGNAL byte_valid : STD_LOGIC;
|
|
SIGNAL xfer_busy : STD_LOGIC;
|
|
SIGNAL bit_cntr : NATURAL;
|
SIGNAL bit_cntr : NATURAL;
|
SIGNAL dll_cntr : NATURAL;
|
SIGNAL dll_cntr : NATURAL;
|
SIGNAL next_state : state_mode;
|
SIGNAL stuffing_det : STD_LOGIC;
|
SIGNAL edge_detect : STD_LOGIC;
|
SIGNAL edge_detect : STD_LOGIC;
|
SIGNAL usb_dp_s0 : STD_LOGIC;
|
SIGNAL usb_dp_s0 : STD_LOGIC;
|
SIGNAL usb_dp_s1 : STD_LOGIC;
|
SIGNAL usb_dp_s1 : STD_LOGIC;
|
SIGNAL usb_dn_s0 : STD_LOGIC;
|
SIGNAL usb_dn_s0 : STD_LOGIC;
|
SIGNAL usb_dn_s1 : STD_LOGIC;
|
SIGNAL usb_dn_s1 : STD_LOGIC;
|
SIGNAL usb_dp_last : STD_LOGIC;
|
SIGNAL usb_dp_last : STD_LOGIC;
|
|
SIGNAL se0 : BOOLEAN;
|
|
|
BEGIN
|
BEGIN
|
|
|
--==========================================================================================================--
|
--==========================================================================================================--
|
-- Synchronize Inputs --
|
-- Synchronize Inputs --
|
--==========================================================================================================--
|
--==========================================================================================================--
|
|
|
|
p_clk_60MHz : PROCESS
|
|
BEGIN
|
|
clk_60MHz <= '0';
|
|
While true loop
|
|
clk_60MHz <= '0';
|
|
WAIT FOR 8333 ps;
|
|
clk_60MHz <= '1';
|
|
WAIT FOR 8334 ps; -- 60 MHz
|
|
end loop;
|
|
END PROCESS;
|
|
|
p_usb_dp_sync: process (clk_60MHz)
|
p_usb_dp_sync: process (clk_60MHz)
|
begin
|
begin
|
if rising_edge(clk_60MHz) then
|
if rising_edge(clk_60MHz) then
|
usb_dp_s0 <= usb_dp;
|
usb_dp_s0 <= usb_dp;
|
usb_dp_s1 <= usb_dp_s0;
|
usb_dp_s1 <= usb_dp_s0;
|
| Line 94... |
Line 107... |
usb_dn_sync <= '0';
|
usb_dn_sync <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
usb_bit <= usb_dp_sync AND NOT usb_dn_sync;
|
|
|
p_usb_d_last: process (clk_60MHz)
|
p_usb_d_last: process (clk_60MHz)
|
begin
|
begin
|
if rising_edge(clk_60MHz) THEN
|
if rising_edge(clk_60MHz) THEN
|
usb_dp_last <= usb_dp_sync;
|
usb_dp_last <= usb_dp_sync;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
edge_detect <= usb_dp_last XOR usb_dp_sync;
|
edge_detect <= usb_dp_last XOR usb_dp_sync;
|
|
|
p_dll_cntr: process (clk_60MHz)
|
p_dll_cntr: PROCESS (clk_60MHz)
|
begin
|
BEGIN
|
if rising_edge(clk_60MHz) then
|
IF rising_edge(clk_60MHz) THEN
|
if edge_detect ='1' then
|
IF edge_detect ='1' THEN
|
if dll_cntr >= 8 then
|
IF dll_cntr >= 8 THEN
|
dll_cntr <= 2; -- clk_en detected, now centered in following cycle
|
dll_cntr <= 2; -- clk_en to be centered in next count sequence
|
else
|
ELSE
|
dll_cntr <= 7; -- adjust clk_en to center cycle
|
dll_cntr <= 7; -- clk_en is now centered
|
end if;
|
END IF;
|
elsif dll_cntr >= 8 then -- normal count sequence is 8->4->5->6->7->8->4...
|
ELSIF dll_cntr >= 8 THEN -- normal count sequence is 8->4->5->6->7->8->4...
|
dll_cntr <= 4;
|
dll_cntr <= 4;
|
else
|
ELSE
|
dll_cntr <= dll_cntr +1;
|
dll_cntr <= dll_cntr +1;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
clk_en <= '1' WHEN dll_cntr >= 8 ELSE '0';
|
clk_en <= '1' WHEN dll_cntr >= 8 ELSE '0';
|
|
|
--==========================================================================================================--
|
--==========================================================================================================--
|
-- Analyse USB Inputs --
|
-- Analyse USB Inputs --
|
--==========================================================================================================--
|
--==========================================================================================================--
|
|
|
|
--se0 <= usb_Dp_sync='0' AND usb_Dn_sync='0';
|
|
|
p_xfer_busy : PROCESS
|
p_se0 : PROCESS(clk_60MHz)
|
VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
BEGIN
|
BEGIN
|
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
|
IF rising_edge(clk_60MHz) THEN
|
sync_pattern := sync_pattern(6 DOWNTO 0) & usb_Dp_sync;
|
IF clk_en ='1' THEN
|
IF sync_pattern = "01010100" THEN
|
se0 <= usb_Dp_sync='0' AND usb_Dn_sync='0';
|
xfer_busy <= '1';
|
END IF;
|
WAIT UNTIL rising_edge(clk_60MHz) AND usb_Dp_sync ='0' AND usb_Dn_sync ='0' AND clk_en ='1';
|
|
END IF;
|
END IF;
|
xfer_busy <= '0';
|
|
END PROCESS;
|
END PROCESS;
|
|
|
p_se0_det : PROCESS
|
p_reset_det : PROCESS(clk_60MHz)
|
VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
VARIABLE se0_lev : BOOLEAN;
|
VARIABLE se0_lev : BOOLEAN;
|
VARIABLE se0_time : Time := 0 ns;
|
VARIABLE se0_time : Time := 0 ns;
|
VARIABLE v_LineWr : line := NULL;
|
VARIABLE v_LineWr : line := NULL;
|
BEGIN
|
BEGIN
|
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
|
IF rising_edge(clk_60MHz) THEN
|
IF usb_Dp_sync ='0' AND usb_Dn_sync ='0' THEN
|
IF clk_en ='1' THEN
|
|
IF se0 THEN
|
IF NOT se0_lev THEN
|
IF NOT se0_lev THEN
|
se0_lev := TRUE;
|
se0_lev := TRUE;
|
se0_time := now;
|
se0_time := now;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
| Line 167... |
Line 180... |
PrintLine(v_LineWr);
|
PrintLine(v_LineWr);
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
se0_lev := FALSE;
|
se0_lev := FALSE;
|
END IF;
|
END IF;
|
|
END IF;
|
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
p_usb_byte : PROCESS(xfer_busy, clk_60MHz, clk_en)
|
p_usb_byte : PROCESS(usb_state, clk_60MHz)
|
VARIABLE hold, usb_last : STD_LOGIC;
|
VARIABLE hold, usb_last : STD_LOGIC;
|
VARIABLE ones_cnt : NATURAL;
|
VARIABLE ones_cnt : NATURAL;
|
BEGIN
|
BEGIN
|
IF xfer_busy ='0' THEN
|
IF rising_edge(clk_60MHz) THEN
|
usb_last := usb_Dp_sync;
|
IF usb_state = idle OR usb_state = eop THEN
|
|
usb_last := usb_bit;
|
bit_cntr <= 0;
|
bit_cntr <= 0;
|
ones_cnt := 0;
|
ones_cnt := 0;
|
byte_valid <= '0';
|
byte_valid <= '0';
|
usb_byte <= (OTHERS => 'H');
|
usb_byte <= (OTHERS => 'H');
|
ELSIF rising_edge(clk_60MHz) AND clk_en ='1' THEN
|
ELSIF clk_en ='1' THEN
|
IF usb_Dp_sync = usb_last THEN
|
IF usb_bit = usb_last THEN
|
usb_byte <= '1' & usb_byte(7 DOWNTO 1);
|
usb_byte <= '1' & usb_byte(7 DOWNTO 1);
|
bit_cntr <= (bit_cntr +1) MOD 8;
|
bit_cntr <= (bit_cntr +1) MOD 8;
|
ones_cnt := (ones_cnt +1);
|
ones_cnt := (ones_cnt +1);
|
IF ones_cnt > 6 THEN
|
IF ones_cnt > 6 THEN
|
ASSERT FALSE REPORT"Stuffing error" SEVERITY ERROR;
|
ASSERT FALSE REPORT"Stuffing error" SEVERITY ERROR;
|
| Line 203... |
Line 219... |
IF bit_cntr=7 THEN
|
IF bit_cntr=7 THEN
|
byte_valid <= NOT hold;
|
byte_valid <= NOT hold;
|
ELSE
|
ELSE
|
byte_valid <= '0';
|
byte_valid <= '0';
|
END IF;
|
END IF;
|
usb_last := usb_Dp_sync;
|
usb_last := usb_bit;
|
END IF;
|
END IF;
|
END PROCESS;
|
stuffing_det <= hold;
|
|
|
p_usb_state : PROCESS
|
|
BEGIN
|
|
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
|
|
IF xfer_busy ='0' THEN
|
|
usb_state <= idle;
|
|
ELSIF usb_Dp_sync ='0' AND usb_Dn_sync ='0' THEN
|
|
usb_state <= eop;
|
|
ELSE
|
|
usb_state <= next_state;
|
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
p_next_state : PROCESS
|
p_usb_state : PROCESS(clk_60MHz)
|
VARIABLE address : STD_LOGIC_VECTOR(6 DOWNTO 0);
|
VARIABLE address : STD_LOGIC_VECTOR(6 DOWNTO 0);
|
VARIABLE endpoint : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
VARIABLE endpoint : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
VARIABLE frame_no : STD_LOGIC_VECTOR(10 DOWNTO 0);
|
VARIABLE frame_no : STD_LOGIC_VECTOR(10 DOWNTO 0);
|
VARIABLE byte_cnt : NATURAL;
|
VARIABLE byte_cnt : NATURAL;
|
|
VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
VARIABLE v_LineWr : line := NULL;
|
VARIABLE v_LineWr : line := NULL;
|
BEGIN
|
BEGIN
|
WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
|
IF rising_edge(clk_60MHz) THEN
|
CASE usb_state IS
|
IF clk_en ='1' THEN
|
WHEN idle => next_state <= pid;
|
IF se0 THEN
|
WHEN pid => IF byte_valid ='1' THEN
|
sync_pattern := (OTHERS => '0');
|
IF usb_byte(3 DOWNTO 0) /= NOT usb_byte(7 DOWNTO 4) THEN
|
ELSE
|
ASSERT FALSE REPORT"PID error" SEVERITY ERROR;
|
sync_pattern := sync_pattern(6 DOWNTO 0) & usb_bit;
|
END IF;
|
END IF;
|
write (v_LineWr, now, right,15);
|
CASE usb_state IS
|
IF master_oe ='1' THEN
|
WHEN idle => IF sync_pattern = "01010100" THEN
|
write (v_LineWr, STRING'(" Send "));
|
usb_state <= pid;
|
ELSE
|
ELSE
|
write (v_LineWr, STRING'(" Recv "));
|
usb_state <= idle;
|
END IF;
|
END IF;
|
byte_cnt := 0;
|
WHEN pid => IF byte_valid ='1' THEN
|
|
IF usb_byte(3 DOWNTO 0) /= NOT usb_byte(7 DOWNTO 4) THEN --+------+------+-------------+
|
|
ASSERT FALSE REPORT"PID error" SEVERITY ERROR; --| PID | usb- | String |
|
|
END IF; --|Bit3:0|state | |
|
|
write (v_LineWr, now, right,15); --|------|------|-------------|
|
|
IF master_oe ='1' THEN --| x"1" | token| "OUT-Token" |
|
|
write (v_LineWr, STRING'(" Send ")); --| x"2" | idle | "ACK" |
|
|
ELSE --| x"3" | data | "Data0" |
|
|
write (v_LineWr, STRING'(" Recv ")); --| x"4" | N/A | "Ping" |
|
|
END IF; --| x"5" | frame| "SOF-Token" |
|
|
byte_cnt := 0; --| x"6" | idle | "NYET" |
|
|
ASSERT usb_byte(3 DOWNTO 0) = NOT usb_byte(7 DOWNTO 4) --| x"7" | data | "Data2" |
|
|
REPORT"PID error detected" SEVERITY ERROR; --| x"8" | N/A | "Split" |
|
|
CASE usb_byte(3 DOWNTO 0) IS --| x"9" | token| "IN-Token" |
|
|
WHEN x"1" => write (v_LineWr, STRING'("OUT-Token")); --| x"A" | idle | "NAK" |
|
|
WHEN x"9" => write (v_LineWr, STRING'("IN-Token")); --| x"B" | data | "Data1" |
|
|
WHEN x"5" => write (v_LineWr, STRING'("SOF-Token")); --| x"C" | N/A | "Preamble" |
|
|
WHEN x"D" => write (v_LineWr, STRING'("Setup")); --| x"D" | token| "Setup" |
|
|
WHEN x"3" => write (v_LineWr, STRING'("Data0")); --| x"E" | idle | "STALL" |
|
|
WHEN x"B" => write (v_LineWr, STRING'("Data1")); --| x"F" | data | "MData" |
|
|
WHEN x"7" => write (v_LineWr, STRING'("Data2")); --| x"0" | idle | "Error" |
|
|
WHEN x"F" => write (v_LineWr, STRING'("MData")); --+------+------+-------------+
|
|
WHEN x"2" => write (v_LineWr, STRING'("ACK"));
|
|
WHEN x"A" => write (v_LineWr, STRING'("NAK"));
|
|
WHEN x"E" => write (v_LineWr, STRING'("STALL"));
|
|
WHEN x"6" => write (v_LineWr, STRING'("NYET"));
|
|
WHEN x"C" => write (v_LineWr, STRING'("Preamble"));
|
|
-- WHEN x"C" => write (v_LineWr, STRING'("SPLIT-ERR"));
|
|
WHEN x"8" => write (v_LineWr, STRING'("Split"));
|
|
WHEN x"4" => write (v_LineWr, STRING'("Ping"));
|
|
WHEN OTHERS => ASSERT FALSE REPORT"PID is zero" SEVERITY ERROR;
|
|
END CASE;
|
CASE usb_byte(3 DOWNTO 0) IS
|
CASE usb_byte(3 DOWNTO 0) IS
|
WHEN x"1" => next_state <= addr;
|
WHEN x"1" | x"9" | x"D" => usb_state <= token1;
|
write (v_LineWr, STRING'("OUT-Token"));
|
WHEN x"5" => usb_state <= frame1;
|
WHEN x"9" => next_state <= addr;
|
WHEN x"3" | x"B" | x"7" | x"F" => usb_state <= data;
|
write (v_LineWr, STRING'("IN-Token"));
|
WHEN x"2" | x"A" | x"E" | x"6" => usb_state <= eop;
|
WHEN x"5" => next_state <= frame;
|
PrintLine(v_LineWr); -- print as soon as possible
|
write (v_LineWr, STRING'("SOF-Token"));
|
WHEN others => usb_state <= idle;
|
WHEN x"D" => next_state <= addr;
|
ASSERT FALSE REPORT "FS-Monitor: This PID is not impemented" SEVERITY WARNING;
|
write (v_LineWr, STRING'("Setup"));
|
|
WHEN x"3" => next_state <= data;
|
|
write (v_LineWr, STRING'("Data0"));
|
|
WHEN x"B" => next_state <= data;
|
|
write (v_LineWr, STRING'("Data1"));
|
|
WHEN x"7" => next_state <= data;
|
|
write (v_LineWr, STRING'("Data2"));
|
|
WHEN x"F" => next_state <= data;
|
|
write (v_LineWr, STRING'("MData"));
|
|
WHEN x"2" => next_state <= idle;
|
|
write (v_LineWr, STRING'("ACK"));
|
|
WHEN x"A" => next_state <= idle;
|
|
write (v_LineWr, STRING'("NAK"));
|
|
WHEN x"E" => next_state <= idle;
|
|
write (v_LineWr, STRING'("STALL"));
|
|
WHEN x"6" => next_state <= idle;
|
|
write (v_LineWr, STRING'("NYET"));
|
|
-- WHEN x"C" => next_state <= spec;
|
|
-- write (v_LineWr, STRING'("Preamble"));
|
|
WHEN x"C" => next_state <= spec;
|
|
write (v_LineWr, STRING'("ERR"));
|
|
WHEN x"8" => next_state <= spec;
|
|
write (v_LineWr, STRING'("Split"));
|
|
WHEN x"4" => next_state <= spec;
|
|
write (v_LineWr, STRING'("Ping"));
|
|
WHEN OTHERS => next_state <= idle;
|
|
ASSERT FALSE REPORT"PID is zero" SEVERITY ERROR;
|
|
END CASE;
|
END CASE;
|
END IF;
|
END IF;
|
WHEN addr => IF byte_valid ='1' THEN
|
IF se0 THEN
|
|
usb_state <= err;
|
|
END IF;
|
|
WHEN token1 => IF byte_valid ='1' THEN
|
address := usb_byte(6 DOWNTO 0);
|
address := usb_byte(6 DOWNTO 0);
|
endpoint(0) := usb_byte(7);
|
endpoint(0) := usb_byte(7);
|
WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1';
|
usb_state <= token2;
|
|
END IF;
|
|
IF se0 THEN
|
|
usb_state <= err;
|
|
END IF;
|
|
WHEN token2 => IF byte_valid ='1' THEN
|
endpoint(3 DOWNTO 1) := usb_byte(2 DOWNTO 0);
|
endpoint(3 DOWNTO 1) := usb_byte(2 DOWNTO 0);
|
write (v_LineWr, STRING'(": Address 0x"));
|
write (v_LineWr, STRING'(": Address 0x"));
|
HexWrite (v_LineWr, address);
|
HexWrite (v_LineWr, address);
|
write (v_LineWr, STRING'(", Endpoint 0x"));
|
write (v_LineWr, STRING'(", Endpoint 0x"));
|
HexWrite (v_LineWr, endpoint);
|
HexWrite (v_LineWr, endpoint);
|
write (v_LineWr, STRING'(", CRC5 0x"));
|
write (v_LineWr, STRING'(", CRC5 0x"));
|
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3));
|
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3));
|
next_state <= idle;
|
usb_state <= eop;
|
|
PrintLine(v_LineWr);
|
END IF;
|
END IF;
|
WHEN frame =>IF byte_valid ='1' THEN
|
WHEN frame1 => IF byte_valid ='1' THEN
|
frame_no(7 DOWNTO 0) := usb_byte;
|
frame_no(7 DOWNTO 0) := usb_byte;
|
WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1';
|
usb_state <= frame2;
|
|
END IF;
|
|
IF se0 THEN
|
|
usb_state <= err;
|
|
END IF;
|
|
WHEN frame2 => IF byte_valid ='1' THEN
|
frame_no(10 DOWNTO 8) := usb_byte(2 DOWNTO 0);
|
frame_no(10 DOWNTO 8) := usb_byte(2 DOWNTO 0);
|
write (v_LineWr, STRING'(": Frame No 0x"));
|
write (v_LineWr, STRING'(": Frame No 0x"));
|
HexWrite (v_LineWr, frame_no);
|
HexWrite (v_LineWr, frame_no);
|
write (v_LineWr, STRING'(", CRC5 0x"));
|
write (v_LineWr, STRING'(", CRC5 0x"));
|
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3));
|
HexWrite (v_LineWr, usb_byte(7 DOWNTO 3));
|
next_state <= idle;
|
usb_state <= err;
|
|
usb_state <= eop;
|
|
PrintLine(v_LineWr);
|
END IF;
|
END IF;
|
WHEN data => WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1';
|
WHEN data => IF byte_valid ='1' THEN
|
byte_cnt := byte_cnt +1;
|
byte_cnt := byte_cnt +1;
|
IF byte_cnt = 17 THEN
|
IF byte_cnt = 17 THEN
|
PrintLine(v_LineWr);
|
PrintLine(v_LineWr);
|
write (v_LineWr, now, right,15);
|
write (v_LineWr, now, right,15);
|
write (v_LineWr, STRING'(" ....."));
|
write (v_LineWr, STRING'(" ....."));
|
byte_cnt := 1;
|
byte_cnt := 1;
|
END IF;
|
END IF;
|
write (v_LineWr, STRING'(" 0x"));
|
write (v_LineWr, STRING'(" 0x"));
|
HexWrite (v_LineWr, usb_byte);
|
HexWrite (v_LineWr, usb_byte);
|
WHEN eop => next_state <= idle;
|
ELSIF se0 THEN
|
PrintLine(v_LineWr);
|
PrintLine(v_LineWr);
|
WHEN OTHERS => next_state <= idle;
|
IF bit_cntr <= 1 THEN
|
|
usb_state <= idle;
|
|
ELSE
|
|
usb_state <= err;
|
|
END IF;
|
|
END IF;
|
|
WHEN eop => IF se0 THEN
|
|
usb_state <= idle;
|
|
ELSIF stuffing_det = '0' THEN
|
|
usb_state <= err;
|
|
END IF;
|
|
WHEN OTHERS => PrintLine(v_LineWr); -- CASE err
|
|
ASSERT FALSE REPORT "FS monitor: protocol error" SEVERITY ERROR;
|
|
usb_state <= idle;
|
END CASE;
|
END CASE;
|
|
END IF;
|
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
usb_busy <= usb_state /= idle; -- global signal, used in usb_commands --
|
usb_busy <= NOT(usb_state = idle OR usb_state = eop); -- global signal, defiened and used in usb_commands --
|
|
|
END SIM;
|
END SIM;
|
|
|
--======================================== END OF usb_fs_monitor.vhd =======================================--
|
--======================================== END OF usb_fs_monitor.vhd =======================================--
|
|
|
No newline at end of file
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No newline at end of file
|
