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Line 36... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: usb1_pd.v,v 1.1.1.1 2002-09-19 12:07:17 rudi Exp $
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// $Id: usb1_pd.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
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//
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//
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// $Date: 2002-09-19 12:07:17 $
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// $Date: 2002-09-25 06:06:49 $
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// $Revision: 1.1.1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2002/09/19 12:07:17 rudi
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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Line 79... |
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// Receive Data Output
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// Receive Data Output
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rx_data_st, rx_data_valid, rx_data_done, crc16_err,
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rx_data_st, rx_data_valid, rx_data_done, crc16_err,
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// Misc.
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// Misc.
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seq_err
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seq_err, rx_busy
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);
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);
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input clk, rst;
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input clk, rst;
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//UTMI RX Interface
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//UTMI RX Interface
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Line 108... |
output rx_data_valid; // Data on rx_data_st is valid
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output rx_data_valid; // Data on rx_data_st is valid
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output rx_data_done; // Indicates end of a transfer
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output rx_data_done; // Indicates end of a transfer
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output crc16_err; // Data packet CRC 16 error
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output crc16_err; // Data packet CRC 16 error
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output seq_err; // State Machine Sequence Error
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output seq_err; // State Machine Sequence Error
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output rx_busy; // Receivig Data Packet
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires and Registers
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// Local Wires and Registers
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//
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//
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Line 168... |
///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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//
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//
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// Misc Logic
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// Misc Logic
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//
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//
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reg rx_busy, rx_busy_d;
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always @(posedge clk or negedge rst)
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if(!rst) rx_busy_d <= #1 1'b0;
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else
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if(rx_valid & (state == DATA)) rx_busy_d <= #1 1'b1;
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else
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if(state != DATA) rx_busy_d <= #1 1'b0;
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always @(posedge clk)
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rx_busy <= #1 rx_busy_d;
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// PID Decoding Logic
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// PID Decoding Logic
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assign pid_ld_en = pid_le_sm & rx_active & rx_valid;
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assign pid_ld_en = pid_le_sm & rx_active & rx_valid;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) pid <= #1 8'hf0;
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if(!rst) pid <= #1 8'hf0;
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