OpenCores

Rev 2	Rev 5
Line 38...	Line 38...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: usb1_pl.v,v 1.1.1.1 2002-09-19 12:07:28 rudi Exp $`	`// $Id: usb1_pl.v,v 1.2 2002-09-25 06:06:49 rudi Exp $`
`//`	`//`
`// $Date: 2002-09-19 12:07:28 $`	`// $Date: 2002-09-25 06:06:49 $`
`// $Revision: 1.1.1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2002/09/19 12:07:28 rudi`
	`// Initial Checkin`
	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
Line 69...	Line 72...
`token_valid,`	`token_valid,`

`// Register File Interface`	`// Register File Interface`
`fa,`	`fa,`
`ep_sel,`	`ep_sel,`
	`x_busy,`
`int_crc16_set, int_to_set, int_seqerr_set,`	`int_crc16_set, int_to_set, int_seqerr_set,`

`// Misc`	`// Misc`
`frm_nat,`	`frm_nat,`
`pid_cs_err, nse_err,`	`pid_cs_err, nse_err,`
`crc5_err,`	`crc5_err,`
`rx_size, rx_done,`	`rx_size, rx_done,`
`ctrl_setup, ctrl_in, ctrl_out,`	`ctrl_setup, ctrl_in, ctrl_out,`

	`// Block Frames`
	`ep_bf_en, ep_bf_size,`
`dropped_frame, misaligned_frame,`	`dropped_frame, misaligned_frame,`

`// EP Interface`	`// EP Interface`
`csr,`	`csr,`
`tx_data_st, rx_data_st, idma_re, idma_we,`	`tx_data_st, rx_data_st, idma_re, idma_we,`
Line 103...	Line 109...
`output token_valid;`	`output token_valid;`

`// Register File interface`	`// Register File interface`
`input [6:0] fa; // Function Address (as set by the controller)`	`input [6:0] fa; // Function Address (as set by the controller)`
`output [3:0] ep_sel; // Endpoint Number Input`	`output [3:0] ep_sel; // Endpoint Number Input`
	`output x_busy; // Indicates USB is busy`

`output int_crc16_set; // Set CRC16 error interrupt`	`output int_crc16_set; // Set CRC16 error interrupt`
`output int_to_set; // Set time out interrupt`	`output int_to_set; // Set time out interrupt`
`output int_seqerr_set; // Set PID sequence error interrupt`	`output int_seqerr_set; // Set PID sequence error interrupt`

Line 118...	Line 125...
`output [7:0] rx_size;`	`output [7:0] rx_size;`
`output rx_done;`	`output rx_done;`
`output ctrl_setup;`	`output ctrl_setup;`
`output ctrl_in;`	`output ctrl_in;`
`output ctrl_out;`	`output ctrl_out;`
	`input ep_bf_en;`
	`input [6:0] ep_bf_size;`
`output dropped_frame, misaligned_frame;`	`output dropped_frame, misaligned_frame;`

`// Endpoint Interfaces`	`// Endpoint Interfaces`
`input [13:0] csr;`	`input [13:0] csr;`
`input [7:0] tx_data_st;`	`input [7:0] tx_data_st;`
Line 190...	Line 199...
`reg ctrl_setup;`	`reg ctrl_setup;`
`reg ctrl_in;`	`reg ctrl_in;`
`reg ctrl_out;`	`reg ctrl_out;`

`wire idma_we_d;`	`wire idma_we_d;`
`wire ep_empty_latched;`	`wire ep_empty_int;`
	`wire rx_busy;`
	`wire tx_busy;`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Misc Logic`	`// Misc Logic`
`//`	`//`

	`assign x_busy = tx_busy \| rx_busy;`

`// PIDs we should never receive`	`// PIDs we should never receive`
`assign pid_bad = pid_ACK \| pid_NACK \| pid_STALL \| pid_NYET \| pid_PRE \|`	`assign pid_bad = pid_ACK \| pid_NACK \| pid_STALL \| pid_NYET \| pid_PRE \|`
`pid_ERR \| pid_SPLIT \| pid_PING;`	`pid_ERR \| pid_SPLIT \| pid_PING;`

`assign match_o = !pid_bad & token_valid & !crc5_err;`	`assign match_o = !pid_bad & token_valid & !crc5_err;`

`// Recieving Setup`	`// Receiving Setup`
`always @(posedge clk)`	`always @(posedge clk)`
`ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);`	`ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);`

`always @(posedge clk)`	`always @(posedge clk)`
`ctrl_in <= #1 token_valid & pid_IN & (ep_sel==4'h0);`	`ctrl_in <= #1 token_valid & pid_IN & (ep_sel==4'h0);`
Line 261...	Line 274...
`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Module Instantiations`	`// Module Instantiations`
`//`	`//`


`//Packet Decoder`	`//Packet Decoder`
`usb1_pd u0( .clk( clk ),`	`usb1_pd u0( .clk( clk ),`
`.rst( rst ),`	`.rst( rst ),`

`.rx_data( rx_data ),`	`.rx_data( rx_data ),`
Line 296...	Line 308...
`.frame_no( frame_no ),`	`.frame_no( frame_no ),`
`.rx_data_st( rx_data_st_d ),`	`.rx_data_st( rx_data_st_d ),`
`.rx_data_valid( rx_data_valid ),`	`.rx_data_valid( rx_data_valid ),`
`.rx_data_done( rx_data_done ),`	`.rx_data_done( rx_data_done ),`
`.crc16_err( crc16_err ),`	`.crc16_err( crc16_err ),`
`.seq_err( rx_seq_err )`	`.seq_err( rx_seq_err ),`
	`.rx_busy( rx_busy )`
`);`	`);`

`// Packet Assembler`	`// Packet Assembler`
`usb1_pa u1( .clk( clk ),`	`usb1_pa u1( .clk( clk ),`
`.rst( rst ),`	`.rst( rst ),`
Line 313...	Line 326...
`.token_pid_sel( token_pid_sel ),`	`.token_pid_sel( token_pid_sel ),`
`.send_data( send_data ),`	`.send_data( send_data ),`
`.data_pid_sel( data_pid_sel ),`	`.data_pid_sel( data_pid_sel ),`
`.tx_data_st( tx_data_st_o ),`	`.tx_data_st( tx_data_st_o ),`
`.rd_next( rd_next ),`	`.rd_next( rd_next ),`
`.ep_empty( ep_empty_latched)`	`.ep_empty( ep_empty_int)`
`);`	`);`

`// Internal DMA / Memory Arbiter Interface`	`// Internal DMA / Memory Arbiter Interface`
`usb1_idma`	`usb1_idma`
`u2( .clk( clk ),`	`u2( .clk( clk ),`
Line 331...	Line 344...

`.tx_data_st_i( tx_data_st ),`	`.tx_data_st_i( tx_data_st ),`
`.tx_data_st_o( tx_data_st_o ),`	`.tx_data_st_o( tx_data_st_o ),`
`.ep_sel( ep_sel ),`	`.ep_sel( ep_sel ),`

	`.ep_bf_en( ep_bf_en ),`
	`.ep_bf_size( ep_bf_size ),`
`.dropped_frame(dropped_frame ),`	`.dropped_frame(dropped_frame ),`
`.misaligned_frame(misaligned_frame),`	`.misaligned_frame(misaligned_frame),`

	`.tx_busy( tx_busy ),`

`.tx_dma_en( tx_dma_en ),`	`.tx_dma_en( tx_dma_en ),`
`.rx_dma_en( rx_dma_en ),`	`.rx_dma_en( rx_dma_en ),`
`.idma_done( idma_done ),`	`.idma_done( idma_done ),`
`.size( csr[8:0] ),`	`.size( csr[8:0] ),`
`.rx_cnt( rx_size ),`	`.rx_cnt( rx_size ),`
`.rx_done( rx_done ),`	`.rx_done( rx_done ),`
`.mwe( idma_we_d ),`	`.mwe( idma_we_d ),`
`.mre( idma_re ),`	`.mre( idma_re ),`
`.ep_empty( ep_empty ),`	`.ep_empty( ep_empty ),`
`.ep_empty_latched(ep_empty_latched),`	`.ep_empty_int( ep_empty_int ),`
`.ep_full( ep_full )`	`.ep_full( ep_full )`
`);`	`);`

`// Protocol Engine`	`// Protocol Engine`
`usb1_pe`	`usb1_pe`
Line 388...	Line 405...
`.int_seqerr_set( int_seqerr_set ),`	`.int_seqerr_set( int_seqerr_set ),`
`.csr( csr ),`	`.csr( csr ),`
`.send_stall( send_stall )`	`.send_stall( send_stall )`
`);`	`);`


`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`

Line 38...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: usb1_pl.v,v 1.1.1.1 2002-09-19 12:07:28 rudi Exp $

//  $Id: usb1_pl.v,v 1.2 2002-09-25 06:06:49 rudi Exp $

//

//

//  $Date: 2002-09-19 12:07:28 $

//  $Date: 2002-09-25 06:06:49 $

//  $Revision: 1.1.1.1 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.1.1.1  2002/09/19 12:07:28  rudi

//               Initial Checkin

//

//

//

//

//

//

//

//

//

//

//

Line 69...

Line 72...

                token_valid,

                token_valid,

                // Register File Interface

                // Register File Interface

fa,

fa,

                ep_sel,

                ep_sel,

                x_busy,

                int_crc16_set, int_to_set, int_seqerr_set,

                int_crc16_set, int_to_set, int_seqerr_set,

                // Misc

                // Misc

                frm_nat,

                frm_nat,

                pid_cs_err, nse_err,

                pid_cs_err, nse_err,

                crc5_err,

                crc5_err,

                rx_size, rx_done,

                rx_size, rx_done,

                ctrl_setup, ctrl_in, ctrl_out,

                ctrl_setup, ctrl_in, ctrl_out,

                // Block Frames

                ep_bf_en, ep_bf_size,

                dropped_frame, misaligned_frame,

                dropped_frame, misaligned_frame,

                // EP Interface

                // EP Interface

                csr,

                csr,

                tx_data_st, rx_data_st, idma_re, idma_we,

                tx_data_st, rx_data_st, idma_re, idma_we,

Line 103...

Line 109...

output          token_valid;

output          token_valid;

// Register File interface

// Register File interface

input   [6:0]    fa;             // Function Address (as set by the controller)

input   [6:0]    fa;             // Function Address (as set by the controller)

output  [3:0]    ep_sel;         // Endpoint Number Input

output  [3:0]    ep_sel;         // Endpoint Number Input

output          x_busy;         // Indicates USB is busy

output          int_crc16_set;  // Set CRC16 error interrupt

output          int_crc16_set;  // Set CRC16 error interrupt

output          int_to_set;     // Set time out interrupt

output          int_to_set;     // Set time out interrupt

output          int_seqerr_set; // Set PID sequence error interrupt

output          int_seqerr_set; // Set PID sequence error interrupt

Line 118...

Line 125...

output  [7:0]    rx_size;

output  [7:0]    rx_size;

output          rx_done;

output          rx_done;

output          ctrl_setup;

output          ctrl_setup;

output          ctrl_in;

output          ctrl_in;

output          ctrl_out;

output          ctrl_out;

input           ep_bf_en;

input   [6:0]    ep_bf_size;

output          dropped_frame, misaligned_frame;

output          dropped_frame, misaligned_frame;

// Endpoint Interfaces

// Endpoint Interfaces

input   [13:0]   csr;

input   [13:0]   csr;

input   [7:0]    tx_data_st;

input   [7:0]    tx_data_st;

Line 190...

Line 199...

reg             ctrl_setup;

reg             ctrl_setup;

reg             ctrl_in;

reg             ctrl_in;

reg             ctrl_out;

reg             ctrl_out;

wire            idma_we_d;

wire            idma_we_d;

wire            ep_empty_latched;

wire            ep_empty_int;

wire            rx_busy;

wire            tx_busy;

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Misc Logic

// Misc Logic

//

//

assign x_busy = tx_busy | rx_busy;

// PIDs we should never receive

// PIDs we should never receive

assign pid_bad = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |

assign pid_bad = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |

                        pid_ERR | pid_SPLIT |  pid_PING;

                        pid_ERR | pid_SPLIT |  pid_PING;

assign match_o = !pid_bad & token_valid & !crc5_err;

assign match_o = !pid_bad & token_valid & !crc5_err;

// Recieving Setup

// Receiving Setup

always @(posedge clk)

always @(posedge clk)

        ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);

        ctrl_setup <= #1 token_valid & pid_SETUP & (ep_sel==4'h0);

always @(posedge clk)

always @(posedge clk)

        ctrl_in <= #1 token_valid & pid_IN & (ep_sel==4'h0);

        ctrl_in <= #1 token_valid & pid_IN & (ep_sel==4'h0);

Line 261...

Line 274...

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Module Instantiations

// Module Instantiations

//

//

//Packet Decoder

//Packet Decoder

usb1_pd u0(     .clk(           clk             ),

usb1_pd u0(     .clk(           clk             ),

                .rst(           rst             ),

                .rst(           rst             ),

                .rx_data(       rx_data         ),

                .rx_data(       rx_data         ),

Line 296...

Line 308...

                .frame_no(      frame_no        ),

                .frame_no(      frame_no        ),

                .rx_data_st(    rx_data_st_d    ),

                .rx_data_st(    rx_data_st_d    ),

                .rx_data_valid( rx_data_valid   ),

                .rx_data_valid( rx_data_valid   ),

                .rx_data_done(  rx_data_done    ),

                .rx_data_done(  rx_data_done    ),

                .crc16_err(     crc16_err       ),

                .crc16_err(     crc16_err       ),

                .seq_err(       rx_seq_err      )

                .seq_err(       rx_seq_err      ),

                .rx_busy(       rx_busy         )

);

);

// Packet Assembler

// Packet Assembler

usb1_pa u1(     .clk(           clk             ),

usb1_pa u1(     .clk(           clk             ),

                .rst(           rst             ),

                .rst(           rst             ),

Line 313...

Line 326...

                .token_pid_sel( token_pid_sel   ),

                .token_pid_sel( token_pid_sel   ),

                .send_data(     send_data       ),

                .send_data(     send_data       ),

                .data_pid_sel(  data_pid_sel    ),

                .data_pid_sel(  data_pid_sel    ),

                .tx_data_st(    tx_data_st_o    ),

                .tx_data_st(    tx_data_st_o    ),

                .rd_next(       rd_next         ),

                .rd_next(       rd_next         ),

                .ep_empty(      ep_empty_latched)

                .ep_empty(      ep_empty_int)

);

);

// Internal DMA / Memory Arbiter Interface

// Internal DMA / Memory Arbiter Interface

usb1_idma

usb1_idma

        u2(     .clk(           clk             ),

        u2(     .clk(           clk             ),

Line 331...

Line 344...

                .tx_data_st_i(  tx_data_st      ),

                .tx_data_st_i(  tx_data_st      ),

                .tx_data_st_o(  tx_data_st_o    ),

                .tx_data_st_o(  tx_data_st_o    ),

                .ep_sel(        ep_sel          ),

                .ep_sel(        ep_sel          ),

                .ep_bf_en(      ep_bf_en        ),

                .ep_bf_size(    ep_bf_size      ),

                .dropped_frame(dropped_frame    ),

                .dropped_frame(dropped_frame    ),

                .misaligned_frame(misaligned_frame),

                .misaligned_frame(misaligned_frame),

                .tx_busy(       tx_busy         ),

                .tx_dma_en(     tx_dma_en       ),

                .tx_dma_en(     tx_dma_en       ),

                .rx_dma_en(     rx_dma_en       ),

                .rx_dma_en(     rx_dma_en       ),

                .idma_done(     idma_done       ),

                .idma_done(     idma_done       ),

                .size(          csr[8:0] ),

                .size(          csr[8:0] ),

                .rx_cnt(        rx_size         ),

                .rx_cnt(        rx_size         ),

                .rx_done(       rx_done         ),

                .rx_done(       rx_done         ),

                .mwe(           idma_we_d       ),

                .mwe(           idma_we_d       ),

                .mre(           idma_re         ),

                .mre(           idma_re         ),

                .ep_empty(      ep_empty        ),

                .ep_empty(      ep_empty        ),

                .ep_empty_latched(ep_empty_latched),

                .ep_empty_int(  ep_empty_int    ),

                .ep_full(       ep_full         )

                .ep_full(       ep_full         )

);

);

// Protocol Engine

// Protocol Engine

usb1_pe

usb1_pe

Line 388...

Line 405...

                .int_seqerr_set(        int_seqerr_set          ),

                .int_seqerr_set(        int_seqerr_set          ),

                .csr(                   csr                     ),

                .csr(                   csr                     ),

                .send_stall(            send_stall              )

                .send_stall(            send_stall              )

);

);

endmodule

endmodule

 No newline at end of file

 No newline at end of file

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