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Line 60... |
-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT lpc_iow
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COMPONENT lpc_iow
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PORT(
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PORT(
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lreset_n : IN std_logic;
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lreset_n : IN std_logic;
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lclk : IN std_logic;
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lclk : IN std_logic;
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lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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lena_reads : in std_logic; --enable read capabilities
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lad_i : IN std_logic_vector(3 downto 0);
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lad_i : IN std_logic_vector(3 downto 0);
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lframe_n : IN std_logic;
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lframe_n : IN std_logic;
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lpc_data_i : IN std_logic_vector(7 downto 0);
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lpc_data_i : IN std_logic_vector(7 downto 0);
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lpc_ack : IN std_logic;
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lpc_ack : IN std_logic;
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lad_o : OUT std_logic_vector(3 downto 0);
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lad_o : OUT std_logic_vector(3 downto 0);
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Line 78... |
END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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SIGNAL lreset_n : std_logic := '0';
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SIGNAL lreset_n : std_logic := '0';
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SIGNAL lclk : std_logic := '0';
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SIGNAL lclk : std_logic := '0';
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SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
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SIGNAL lframe_n : std_logic := '1';
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SIGNAL lframe_n : std_logic := '1';
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SIGNAL lpc_ack : std_logic := '0';
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SIGNAL lpc_ack : std_logic := '0';
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SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
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SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
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SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
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SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
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Line 101... |
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: lpc_iow PORT MAP(
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uut: lpc_iow PORT MAP(
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lreset_n => lreset_n,
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lreset_n => lreset_n,
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lclk => lclk,
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lclk => lclk,
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lena_mem_r=> lena_mem_r,
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lena_reads => lena_reads,
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lad_i => lad_i,
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lad_i => lad_i,
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lad_o => lad_o,
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lad_o => lad_o,
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lad_oe => lad_oe,
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lad_oe => lad_oe,
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lframe_n => lframe_n,
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lframe_n => lframe_n,
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lpc_addr => lpc_addr,
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lpc_addr => lpc_addr,
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Line 171... |
wait until lclk='0'; --cycle 9
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wait until lclk='0'; --cycle 9
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wait until lclk='1';
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wait until lclk='1';
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lad_i <=x"F"; --TAR 1
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lad_i <=x"F"; --TAR 1
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wait until lclk='0'; --cycle 10
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wait until lclk='0'; --cycle 10
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wait until lclk='1';
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wait until lclk='1';
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if lad_o=x"F" and lad_oe='1' then --TAR 2
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if lad_oe='0' then --TAR 2
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else
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else
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report "LPC error found on TAR cycle no 0xF on lad_o";
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report "LPC error found on TAR cycle no 0xF on lad_o";
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lframe_n <='0';
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lframe_n <='0';
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end if;
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end if;
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wait until lclk='0'; --cycle 11
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wait until lclk='0'; --cycle 11
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wait until lclk='1';
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wait until lclk='1';
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wait until lad_o=x"6";
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while(lad_o=x"6") loop
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wait until lclk='0'; --cycle 11
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wait until lclk='1';
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end loop;
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if (lad_o=x"0") and lad_oe='1' then --SYNC
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if (lad_o=x"0") and lad_oe='1' then --SYNC
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else
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else
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report "LPC error found on SYNC cycle no 0x0 on lad_o";
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report "LPC error found on SYNC cycle no 0x0 on lad_o";
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lframe_n <='0';
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lframe_n <='0';
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end if;
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end if;
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