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entity design_top is
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entity design_top is
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port (
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port (
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--system signals
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--system signals
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sys_clk : in std_logic; --25 MHz clk
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sys_clk : in std_logic; --25 MHz clk
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resetn : in std_logic;
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resetn : in std_logic;
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hdr : out std_logic_vector(10 downto 0);
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hdr : inout std_logic_vector(10 downto 0);
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--alt_clk : out std_logic; --alternative clock from extention header
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--alt_clk : out std_logic;
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mode : in std_logic_vector(1 downto 0); --sel upper addr bits
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mode : in std_logic_vector(1 downto 0); --sel upper addr bits
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--lpc slave interf
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--lpc slave interf
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lad : inout std_logic_vector(3 downto 0);
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lad : inout std_logic_vector(3 downto 0);
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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| Line 117... |
Line 117... |
component lpc_iow
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component lpc_iow
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port (
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port (
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--system signals
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--system signals
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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lclk : in std_logic;
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lclk : in std_logic;
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lena_mem_r : in std_logic; --enable full adress range covering memory read block
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lena_reads : in std_logic; --enable read capabilities
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--LPC bus from host
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--LPC bus from host
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lad_i : in std_logic_vector(3 downto 0);
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lad_i : in std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_oe : out std_logic;
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lad_oe : out std_logic;
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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signal lpc_data_o : std_logic_vector(7 downto 0);
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signal lpc_data_o : std_logic_vector(7 downto 0);
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signal lpc_data_i : std_logic_vector(7 downto 0);
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signal lpc_data_i : std_logic_vector(7 downto 0);
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signal lpc_wr : std_logic; --shared write not read
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signal lpc_wr : std_logic; --shared write not read
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signal lpc_ack : std_logic;
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signal lpc_ack : std_logic;
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signal lpc_val : std_logic;
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signal lpc_val : std_logic;
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signal lena_mem_r : std_logic; --enable full adress range covering memory read block
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signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
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signal c25_lpc_val : std_logic;
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signal c25_lpc_val : std_logic;
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signal c25_lpc_wr : std_logic; --shared write not read
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signal c25_lpc_wr : std_logic; --shared write not read
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signal c33_lpc_wr : std_logic; --for led debug data latching
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signal c33_lpc_wr : std_logic; --for led debug data latching
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signal enable_4meg: std_logic;
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signal enable_4meg: std_logic;
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--END USB signals
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--END USB signals
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begin
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begin
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--GPIO PINS START
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hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header)
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hdr(0) <= 'Z';
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lena_mem_r <= not hdr(0); -- disabled if jumper is not on header pins 1-2
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lena_reads <= hdr(3); -- disabled if jumper is on (jumper makes it a postcode only device)
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--GPIO PINS END
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--LED SUBSYSTEM START
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--LED SUBSYSTEM START
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data_to_disp <= x"86"&lpc_debug(7 downto 0); --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
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data_to_disp <= x"86"&lpc_debug(7 downto 0); --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
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LEDS: led_sys --toplevel for led system
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LEDS: led_sys --toplevel for led system
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generic map(
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generic map(
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msn_hib => "01111111",--8 --Most signif. of hi byte
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msn_hib => "01111111",--8 --Most signif. of hi byte
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lsn_hib => "01111101",--6 --Least signif. of hi byte
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lsn_hib => "01111101",--6 --Least signif. of hi byte
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msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
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msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
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lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
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--lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
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lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
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)
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)
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port map(
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port map(
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clk => sys_clk , -- in std_logic;
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clk => sys_clk , -- in std_logic;
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reset_n => resetn, -- in std_logic;
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reset_n => resetn, -- in std_logic;
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led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
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led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
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Line 287... |
LPCBUS : lpc_iow
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LPCBUS : lpc_iow
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port map(
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port map(
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--system signals
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--system signals
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lreset_n => lreset_n, -- in std_logic;
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lreset_n => lreset_n, -- in std_logic;
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lclk => lclk, -- in std_logic;
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lclk => lclk, -- in std_logic;
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lena_mem_r => lena_mem_r,--: in std_logic; --enable full adress range covering memory read block
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lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
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--LPC bus from host
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--LPC bus from host
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lad_i => lad_i, -- in std_logic_vector(3 downto 0);
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lad_i => lad_i, -- in std_logic_vector(3 downto 0);
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lad_o => lad_o, -- out std_logic_vector(3 downto 0);
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lad_o => lad_o, -- out std_logic_vector(3 downto 0);
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lad_oe => lad_oe, -- out std_logic;
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lad_oe => lad_oe, -- out std_logic;
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lframe_n => lframe_n, -- in std_logic;
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lframe_n => lframe_n, -- in std_logic;
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Line 406... |
mem_wr => mem_wr, -- in std_logic; --write not read signal
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mem_wr => mem_wr, -- in std_logic; --write not read signal
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mem_val => mem_val, -- in std_logic;
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mem_val => mem_val, -- in std_logic;
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mem_ack => mem_ack -- out std_logic
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mem_ack => mem_ack -- out std_logic
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);
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);
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--hdr(7 downto 0) <= umem_do(7 downto 0) when umem_ack='0' and umem_wr='1' else
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-- umem_do(15 downto 8) when umem_ack='1' and umem_wr='1' else
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-- mem_do(7 downto 0) when umem_wr='0' else
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-- mem_do(15 downto 8);
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--hdr(8)<= umem_wr;
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--hdr(9)<= umem_val;
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--hdr(10)<= umem_ack;
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-- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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-- usb_wr : out std_logic; -- write performed on edge \ of signal
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-- usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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-- usb_rxf_n : in std_logic; -- rx fifo has data if low
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hdr(3 downto 0) <= lad_o when lad_oe='1' else
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lad;
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hdr(4)<= lframe_n;
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hdr(5)<= lreset_n;
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hdr(6)<= lclk;
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hdr(7)<= lpc_ack;
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--hdr(7 downto 0) <= lpc_data_o(7 downto 0);
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hdr(8)<= lpc_val;
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hdr(9)<= '1' when lpc_wr='1' and lpc_addr(7 downto 0)=x"88" else
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'0';
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hdr(10)<= resetn;
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USB: usb2mem
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USB: usb2mem
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port map(
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port map(
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clk25 => sys_clk, -- in std_logic;
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clk25 => sys_clk, -- in std_logic;
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