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[/] [usb_dongle_fpga/] [tags/] [version_1_5/] [src/] [lpc_proto/] [lpc_byte.vhd] - Diff between revs 18 and 19

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Rev 18 Rev 19
Line 107... Line 107...
    data_valid <='1';
    data_valid <='1';
    lad_rising_o<="0000";
    lad_rising_o<="0000";
    lpc_val <='0';
    lpc_val <='0';
        lpc_wr <='0';
        lpc_wr <='0';
        r_lad <= (others=>'0');
        r_lad <= (others=>'0');
        cycle_type <= (others=>'0');
        cycle_type <= LPC_IO_W; --initial value 
        r_addr <= (others=>'0');
        r_addr <= (others=>'0');
        r_cnt <= (others=>'0');
        r_cnt <= (others=>'0');
   elsif lclk'event and lclk = '1' then  -- rising clock edge
   elsif lclk'event and lclk = '1' then  -- rising clock edge
    case CS is
    case CS is
      when RESETs => ----------------------------------------------------------
      when RESETs => ----------------------------------------------------------

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