| Line 60... |
Line 60... |
-- Component Declaration for the Unit Under Test (UUT)
|
-- Component Declaration for the Unit Under Test (UUT)
|
COMPONENT lpc_iow
|
COMPONENT lpc_iow
|
PORT(
|
PORT(
|
lreset_n : IN std_logic;
|
lreset_n : IN std_logic;
|
lclk : IN std_logic;
|
lclk : IN std_logic;
|
|
lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
|
|
lena_reads : in std_logic; --enable read capabilities
|
lad_i : IN std_logic_vector(3 downto 0);
|
lad_i : IN std_logic_vector(3 downto 0);
|
lframe_n : IN std_logic;
|
lframe_n : IN std_logic;
|
lpc_data_i : IN std_logic_vector(7 downto 0);
|
lpc_data_i : IN std_logic_vector(7 downto 0);
|
lpc_ack : IN std_logic;
|
lpc_ack : IN std_logic;
|
lad_o : OUT std_logic_vector(3 downto 0);
|
lad_o : OUT std_logic_vector(3 downto 0);
|
| Line 76... |
Line 78... |
END COMPONENT;
|
END COMPONENT;
|
|
|
--Inputs
|
--Inputs
|
SIGNAL lreset_n : std_logic := '0';
|
SIGNAL lreset_n : std_logic := '0';
|
SIGNAL lclk : std_logic := '0';
|
SIGNAL lclk : std_logic := '0';
|
|
|
|
SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
|
|
SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
|
|
|
SIGNAL lframe_n : std_logic := '1';
|
SIGNAL lframe_n : std_logic := '1';
|
SIGNAL lpc_ack : std_logic := '0';
|
SIGNAL lpc_ack : std_logic := '0';
|
SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
|
SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
|
SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
|
SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
|
|
|
| Line 95... |
Line 101... |
|
|
-- Instantiate the Unit Under Test (UUT)
|
-- Instantiate the Unit Under Test (UUT)
|
uut: lpc_iow PORT MAP(
|
uut: lpc_iow PORT MAP(
|
lreset_n => lreset_n,
|
lreset_n => lreset_n,
|
lclk => lclk,
|
lclk => lclk,
|
|
lena_mem_r=> lena_mem_r,
|
|
lena_reads => lena_reads,
|
lad_i => lad_i,
|
lad_i => lad_i,
|
lad_o => lad_o,
|
lad_o => lad_o,
|
lad_oe => lad_oe,
|
lad_oe => lad_oe,
|
lframe_n => lframe_n,
|
lframe_n => lframe_n,
|
lpc_addr => lpc_addr,
|
lpc_addr => lpc_addr,
|
| Line 163... |
Line 171... |
wait until lclk='0'; --cycle 9
|
wait until lclk='0'; --cycle 9
|
wait until lclk='1';
|
wait until lclk='1';
|
lad_i <=x"F"; --TAR 1
|
lad_i <=x"F"; --TAR 1
|
wait until lclk='0'; --cycle 10
|
wait until lclk='0'; --cycle 10
|
wait until lclk='1';
|
wait until lclk='1';
|
if lad_o=x"F" and lad_oe='1' then --TAR 2
|
if lad_oe='0' then --TAR 2
|
else
|
else
|
report "LPC error found on TAR cycle no 0xF on lad_o";
|
report "LPC error found on TAR cycle no 0xF on lad_o";
|
lframe_n <='0';
|
lframe_n <='0';
|
end if;
|
end if;
|
wait until lclk='0'; --cycle 11
|
wait until lclk='0'; --cycle 11
|
wait until lclk='1';
|
wait until lclk='1';
|
|
wait until lad_o=x"6";
|
|
while(lad_o=x"6") loop
|
|
wait until lclk='0'; --cycle 11
|
|
wait until lclk='1';
|
|
end loop;
|
if (lad_o=x"0") and lad_oe='1' then --SYNC
|
if (lad_o=x"0") and lad_oe='1' then --SYNC
|
else
|
else
|
report "LPC error found on SYNC cycle no 0x0 on lad_o";
|
report "LPC error found on SYNC cycle no 0x0 on lad_o";
|
lframe_n <='0';
|
lframe_n <='0';
|
end if;
|
end if;
|
