URL https://opencores.org/ocsvn/usb_dongle_fpga/usb_dongle_fpga/trunk

Subversion Repositories usb_dongle_fpga

[/] [usb_dongle_fpga/] [trunk/] [src/] [design_top/] [design_top_thincandbg.vhd] - Diff between revs 2 and 15

Rev 2	Rev 15
Line 250...	Line 250...
`LEDS: led_sys --toplevel for led system`	`LEDS: led_sys --toplevel for led system`
`generic map(`	`generic map(`
`msn_hib => "01111111",--8 --Most signif. of hi byte`	`msn_hib => "01111111",--8 --Most signif. of hi byte`
`lsn_hib => "01111101",--6 --Least signif. of hi byte`	`lsn_hib => "01111101",--6 --Least signif. of hi byte`
`msn_lob => "10111111",--0 --Most signif. of hi byte This is version code`	`msn_lob => "10111111",--0 --Most signif. of hi byte This is version code`
`lsn_lob => "01011011" --2 --Least signif. of hi byte This is version code`	`lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code`
`)`	`)`
`port map(`	`port map(`
`clk => sys_clk , -- in std_logic;`	`clk => sys_clk , -- in std_logic;`
`reset_n => resetn, -- in std_logic;`	`reset_n => resetn, -- in std_logic;`
`led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in`	`led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in`
Line 266...	Line 266...


`--MAIN DATAPATH CONNECTIONS`	`--MAIN DATAPATH CONNECTIONS`
`--LPC bus logic`	`--LPC bus logic`
`lad_i <= lad;`	`lad_i <= lad;`
`lad <= lad_o when lad_oe='1' and mode/="00" else --mode "00" is post code spy mode`	`lad <= lad_o when lad_oe='1' else`
`(others=>'Z');`	`(others=>'Z');`

`--END LPC bus logic`	`--END LPC bus logic`

`LPCBUS : lpc_iow`	`LPCBUS : lpc_iow`