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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity design_top is
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entity design_top_thincandbg is
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port (
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port (
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--system signals
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--system signals
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sys_clk : in std_logic; --25 MHz clk
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sys_clk : in std_logic; --25 MHz clk
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resetn : in std_logic;
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resetn : in std_logic;
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hdr : inout std_logic_vector(9 downto 0);
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hdr : inout std_logic_vector(9 downto 0);
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| Line 90... |
Line 90... |
usb_wr : inout std_logic; -- write performed on edge \ of signal
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usb_wr : inout std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo has data if low
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usb_rxf_n : in std_logic; -- rx fifo has data if low
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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);
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);
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end design_top;
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end design_top_thincandbg;
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architecture rtl of design_top is
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architecture rtl of design_top_thincandbg is
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component led_sys --toplevel for led system
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component led_sys --toplevel for led system
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generic(
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generic(
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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Line 264... |
signal dbg_wr : STD_LOGIC; --write not read
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signal dbg_wr : STD_LOGIC; --write not read
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signal dbg_full : STD_LOGIC; --write not read
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signal dbg_full : STD_LOGIC; --write not read
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signal dbg_almost_full : STD_LOGIC;
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signal dbg_almost_full : STD_LOGIC;
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signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
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signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
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signal force_4meg_n : std_logic;
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signal dbg_usb_mode_en : std_logic;
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signal dbg_usb_mode_en : std_logic;
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signal usb_mode_en : std_logic;
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signal usb_mode_en : std_logic;
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signal mem_idle : std_logic;
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signal mem_idle : std_logic;
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signal umem_addr : std_logic_vector(23 downto 0);
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signal umem_addr : std_logic_vector(23 downto 0);
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signal umem_do : std_logic_vector(15 downto 0);
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signal umem_do : std_logic_vector(15 downto 0);
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signal umem_ack : std_logic;
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signal umem_ack : std_logic;
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signal umem_cmd : std_logic;
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signal umem_cmd : std_logic;
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signal enable_4meg: std_logic;
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signal enable_4meg: std_logic;
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signal dongle_con_n : std_logic;
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signal dongle_con_n : std_logic;
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constant dongle_ver : std_logic_vector(15 downto 0):=x"8605";
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constant dongle_ver : std_logic_vector(15 downto 0):=x"8606";
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--END USB signals
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--END USB signals
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begin
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begin
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--GPIO PINS START
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--GPIO PINS START
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-- when jumper on pins 7,8 then post code capture mode enabled
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-- when jumper on pins 7,8 then post code capture mode enabled
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hdr(4)<= '0';
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hdr(4)<= '0';
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dbg_usb_mode_en <= not hdr(5); --weak pullup on hdr(5) paired with hdr(4)
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dbg_usb_mode_en <= not hdr(5); --weak pullup on hdr(5) paired with hdr(4)
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usb_mode_en <= not dbg_usb_mode_en;
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usb_mode_en <= not dbg_usb_mode_en;
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-- when jumper on pins 9,10 then 4M window is forced
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hdr(6)<= '0';
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force_4meg_n <= hdr(7); --weak pullup on hdr(7) paired with hdr(6)
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--GPIO PINS END
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--GPIO PINS END
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--LED SUBSYSTEM START
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--LED SUBSYSTEM START
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data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
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data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
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"000"&dbg_usedw; --show tx fifo state on leds when postcode capture mode
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"000"&dbg_usedw; --show tx fifo state on leds when postcode capture mode
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msn_hib => "01111111",--8 --Most signif. of hi byte
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msn_hib => "01111111",--8 --Most signif. of hi byte
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lsn_hib => "01111101",--6 --Least signif. of hi byte
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lsn_hib => "01111101",--6 --Least signif. of hi byte
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msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
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msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
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--lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
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--lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
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--lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
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--lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
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lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
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--lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
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lsn_lob => "01111101" --6 --sync with dongle version const. Least signif. of hi byte This is version code
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)
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)
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port map(
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port map(
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clk => sys_clk , -- in std_logic;
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clk => sys_clk , -- in std_logic;
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reset_n => resetn, -- in std_logic;
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reset_n => resetn, -- in std_logic;
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elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
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elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
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dongle_con_n <='1'; -- pin 3 in GPIO make it 1
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dongle_con_n <='1'; -- pin 3 in GPIO make it 1
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elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
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elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
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dongle_con_n <='0'; -- pin 3 in GPIO make it 1
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dongle_con_n <='0'; -- pin 3 in GPIO make it 1
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end if;
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end if;
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else
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if force_4meg_n='0' then -- active low (always force when jumper on)
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enable_4meg <='1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process LATCHled;
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end process LATCHled;
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