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[/] [usb_dongle_fpga/] [trunk/] [src/] [lpc_proto/] [lpc_byte.vhd] - Diff between revs 17 and 18

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Rev 17 Rev 18
Line 105... Line 105...
    CS<= RESETs;
    CS<= RESETs;
    lad_rising_oe<='0';
    lad_rising_oe<='0';
    data_valid <='1';
    data_valid <='1';
    lad_rising_o<="0000";
    lad_rising_o<="0000";
    lpc_val <='0';
    lpc_val <='0';
 
        lpc_wr <='0';
 
        r_lad <= (others=>'0');
 
        cycle_type <= (others=>'0');
        r_addr <= (others=>'0');
        r_addr <= (others=>'0');
 
        r_cnt <= (others=>'0');
   elsif lclk'event and lclk = '1' then  -- rising clock edge
   elsif lclk'event and lclk = '1' then  -- rising clock edge
    case CS is
    case CS is
      when RESETs => ----------------------------------------------------------
      when RESETs => ----------------------------------------------------------
        lpc_wr <='0';
        lpc_wr <='0';
        lpc_val <='0';
        lpc_val <='0';

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