| Line 35... |
Line 35... |
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entity usb2mem is
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entity usb2mem is
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port (
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port (
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clk25 : in std_logic;
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clk25 : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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dongle_ver: in std_logic_vector(15 downto 0);
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-- mem Bus
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-- mem Bus
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mem_busy_n : in std_logic;
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mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
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mem_addr : out std_logic_vector(23 downto 0);
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mem_addr : out std_logic_vector(23 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_do : out std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_di : in std_logic_vector(15 downto 0);
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mem_wr : out std_logic;
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mem_wr : out std_logic;
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mem_val : out std_logic;
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mem_val : out std_logic;
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mem_ack : in std_logic;
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mem_ack : in std_logic;
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mem_cmd : out std_logic;
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mem_cmd : out std_logic;
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-- USB port
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-- USB port
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usb_mode_en: in std_logic; -- enable this block
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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| Line 58... |
Line 62... |
architecture RTL of usb2mem is
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architecture RTL of usb2mem is
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type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s);
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type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s,STS_WAITs);
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signal CS : state_type;
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signal CS : state_type;
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signal data_reg_i : std_logic_vector(15 downto 0);
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signal data_reg_i : std_logic_vector(15 downto 0);
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signal data_reg_o : std_logic_vector(15 downto 0);
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signal data_reg_o : std_logic_vector(15 downto 0);
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signal data_oe : std_logic; -- rx fifo empty (data redy if low)
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signal data_oe : std_logic; -- rx fifo empty (data redy if low)
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signal usb_wr_d : std_logic; -- internal readable output state for write
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signal usb_wr_d : std_logic; -- internal readable output state for write
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signal addr_reg: std_logic_vector(23 downto 0);
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signal addr_reg: std_logic_vector(23 downto 0);
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--State machine
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--State machine
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signal cmd_cnt : std_logic_vector(7 downto 0);
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signal cmd_cnt : std_logic_vector(15 downto 0);
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signal state_cnt : std_logic_vector(3 downto 0);
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signal state_cnt : std_logic_vector(3 downto 0);
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--shyncro to USB
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--shyncro to USB
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signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
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signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
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signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
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signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
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signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
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signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
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signal read_mode : std_logic;
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signal read_mode : std_logic;
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signal write_mode : std_logic;
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signal write_mode : std_logic;
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signal write_count : std_logic;
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signal write_count : std_logic;
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signal first_word : std_logic;
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signal first_word : std_logic;
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signal mem_busy_nd : std_logic;
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begin
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begin
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| Line 96... |
Line 101... |
--These are spechial attention Flash commands
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--These are spechial attention Flash commands
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'1' when data_reg_i(7 downto 0) = x"E8" else
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'1' when data_reg_i(7 downto 0) = x"E8" else
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'0';
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'0';
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usb_wr <= usb_wr_d;
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usb_wr <= usb_wr_d when usb_mode_en='1' else
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'Z';
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-- this goes to byte buffer for that reason send LSB first and MSB second
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-- this goes to byte buffer for that reason send LSB first and MSB second
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usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s else --LSB byte first
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usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first
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data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s else --MSB byte second
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data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else --MSB byte second
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(others=>'Z');
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(others=>'Z');
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process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
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process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
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begin -- process
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begin -- process
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| Line 125... |
Line 132... |
cmd_cnt <= (others=>'0');
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cmd_cnt <= (others=>'0');
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read_mode <='0';
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read_mode <='0';
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write_mode <='0';
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write_mode <='0';
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write_count <='0';
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write_count <='0';
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first_word <='0';
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first_word <='0';
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mem_idle <='1'; --set idle
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mem_busy_nd <='1';
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elsif clk25'event and clk25 = '1' then -- rising clock edge
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elsif clk25'event and clk25 = '1' then -- rising clock edge
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usb_txe_nd <= usb_txe_n;
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usb_txe_nd <= usb_txe_n; --syncronize
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usb_rxf_nd <= usb_rxf_n;
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usb_rxf_nd <= usb_rxf_n; --syncronize
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mem_busy_nd <=mem_busy_n; --syncronize
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case CS is
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case CS is
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when RESETs =>
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when RESETs =>
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if usb_rxf_nd='0' then
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if usb_rxf_nd='0' and usb_mode_en='1' and mem_busy_nd='1' then
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state_cnt <=(others=>'0'); --init command counter
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state_cnt <=(others=>'0'); --init command counter
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data_oe <='0'; --we will read command in
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data_oe <='0'; --we will read command in
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mem_idle <='0'; --set busy untill return here
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CS <= RXCMD0s;
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CS <= RXCMD0s;
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elsif mem_busy_nd='1' then
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mem_idle <='1'; --set idle when here
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end if;
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end if;
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when RXCMD0s =>
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when RXCMD0s =>
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if state_cnt="0000" then
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if state_cnt="0000" then
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usb_rd_n <='0'; -- set read low
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usb_rd_n <='0'; -- set read low
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state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
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state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
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| Line 182... |
Line 195... |
else
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else
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state_cnt <=(others=>'0'); --init command counter
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state_cnt <=(others=>'0'); --init command counter
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CS <= INTERNs;
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CS <= INTERNs;
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end if;
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end if;
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when INTERNs =>
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when INTERNs =>
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if cmd_cnt=x"00" then
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if cmd_cnt=x"0000" then
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if data_reg_i(7 downto 0)=x"A0" then
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if data_reg_i(7 downto 0)=x"A0" then
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addr_reg(7 downto 0)<= data_reg_i(15 downto 8);
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addr_reg(7 downto 0)<= data_reg_i(15 downto 8);
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CS <= RESETs; --go back to resets
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CS <= RESETs; --go back to resets
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elsif data_reg_i(7 downto 0)=x"A1" then
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elsif data_reg_i(7 downto 0)=x"A1" then
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addr_reg(15 downto 8)<= data_reg_i(15 downto 8);
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addr_reg(15 downto 8)<= data_reg_i(15 downto 8);
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| Line 195... |
Line 208... |
addr_reg(23 downto 16)<= data_reg_i(15 downto 8);
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addr_reg(23 downto 16)<= data_reg_i(15 downto 8);
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CS <= RESETs; --go back to resets
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CS <= RESETs; --go back to resets
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elsif data_reg_i(7 downto 0)=x"3F" then
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elsif data_reg_i(7 downto 0)=x"3F" then
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CS <= RESETs; --go back to resets --NOP command
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CS <= RESETs; --go back to resets --NOP command
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elsif data_reg_i(7 downto 0)=x"C5" then
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elsif data_reg_i(7 downto 0)=x"C5" then
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if (data_reg_i(15 downto 8))=x"00" then
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data_reg_o <=x"3210";
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data_reg_o <=x"3210";
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else
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data_reg_o <=dongle_ver;
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end if;
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CS <= TXCMD0s;
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CS <= TXCMD0s;
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elsif data_reg_i(7 downto 0)=x"CD" then
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elsif data_reg_i(7 downto 0)=x"CD" then
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cmd_cnt <= data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now
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if (data_reg_i(15 downto 8))=x"00" then --64K word read coming
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cmd_cnt <= (others=>'1'); --64K word count
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else
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cmd_cnt <= x"00"&data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now (cmd_cnt words)
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end if;
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CS <= VCIRDs; --go perform a read
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CS <= VCIRDs; --go perform a read
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read_mode <='1';
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read_mode <='1';
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elsif data_reg_i(7 downto 0)=x"E8" then
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elsif data_reg_i(7 downto 0)=x"E8" then
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--write_mode <='1';
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--write_mode <='1';
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write_count <='0';
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write_count <='0';
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first_word <='0';
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first_word <='0';
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cmd_cnt <= data_reg_i(15 downto 8) + 1; --+2 for direct count write +1
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cmd_cnt <= x"00"&data_reg_i(15 downto 8) + 1; --+2 for direct count write +1
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data_reg_i(15 downto 8)<=(others=>'0');
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data_reg_i(15 downto 8)<=(others=>'0');
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CS <= VCIWRs; --go perform a write
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CS <= VCIWRs; --go perform a write
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else
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else
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CS <= VCIWRs;
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CS <= VCIWRs;
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end if;
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end if;
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else
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else
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if cmd_cnt>x"00" then
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if cmd_cnt>x"0000" then
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cmd_cnt<= cmd_cnt - 1;
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cmd_cnt<= cmd_cnt - 1;
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if write_count='0' then
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if write_count='0' then
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write_count<='1';
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write_count<='1';
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elsif write_count='1' and first_word ='0' then
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elsif write_count='1' and first_word ='0' then
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first_word <='1';
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first_word <='1';
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| Line 250... |
Line 271... |
if mem_ack='1' then
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if mem_ack='1' then
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mem_do <= (others=>'Z');
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mem_do <= (others=>'Z');
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mem_wr <='0'; --this is VCI write_not_read
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mem_wr <='0'; --this is VCI write_not_read
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mem_cmd <='0';
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mem_cmd <='0';
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mem_val <= '0';
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mem_val <= '0';
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if write_mode='0' then
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--if write_mode='0' then
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if cmd_cnt=x"0000" then --if flash command and not data
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state_cnt <=(others=>'0'); --init command counter
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CS <= STS_WAITs;
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else
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CS <= RESETs;
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CS <= RESETs;
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end if;
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--else --else if was 0xE8 must read and return XSR
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--else --else if was 0xE8 must read and return XSR
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-- write_mode <='0'; --XSR return will no follow clear this bit
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-- write_mode <='0'; --XSR return will no follow clear this bit
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-- CS <= VCIRDs;
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-- CS <= VCIRDs;
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end if;
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--end if;
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end if;
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end if;
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when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first
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when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first
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if state_cnt="0000" then
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if state_cnt="0000" then
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if usb_txe_nd='0' then
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if usb_txe_nd='0' then
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| Line 299... |
Line 326... |
state_cnt <= state_cnt + 1;-- now is ok
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state_cnt <= state_cnt + 1;-- now is ok
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data_oe<='0';
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data_oe<='0';
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elsif state_cnt="0111" then --must stay low at least 50ns
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elsif state_cnt="0111" then --must stay low at least 50ns
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if read_mode='0' then
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if read_mode='0' then
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CS <= RESETs;
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CS <= RESETs;
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elsif cmd_cnt="00" then --last word sent
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elsif cmd_cnt="0000" then --last word sent
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addr_reg <= addr_reg + 1; --autoincrement address in read mode
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addr_reg <= addr_reg + 1; --autoincrement address in read mode
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read_mode <='0';
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read_mode <='0';
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CS <= RESETs;
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CS <= RESETs;
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else
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else
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cmd_cnt<= cmd_cnt - 1;
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cmd_cnt<= cmd_cnt - 1;
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| Line 312... |
Line 339... |
end if;
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end if;
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state_cnt <= (others=>'0');
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state_cnt <= (others=>'0');
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else
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else
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state_cnt <= state_cnt + 1;-- if intermediate cnt then count
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state_cnt <= state_cnt + 1;-- if intermediate cnt then count
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end if;
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end if;
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when STS_WAITs =>
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if mem_busy_nd='0' then
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CS <= RESETs; --now it's ok to go here
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else
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state_cnt <= state_cnt + 1;
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if state_cnt="1111" then
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--sts cant take longer than 500 ns to go low
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CS <= RESETs; --time out go to resets anyway
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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