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https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk
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CLK : in std_logic
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CLK : in std_logic
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);
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);
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end ucecho;
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end ucecho;
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--signal declaration
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architecture RTL of ucecho is
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architecture RTL of ucecho is
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--signal declaration
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signal pb_buf : unsigned(7 downto 0);
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begin
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begin
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dpUCECHO: process(CLK)
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dpUCECHO: process(CLK)
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begin
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begin
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if CLK' event and CLK = '1' then
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if CLK' event and CLK = '1' then
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if ( pc >= 97 ) and ( pc <= 122)
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if ( pc >= 97 ) and ( pc <= 122)
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then
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then
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pb <= pc - 32;
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pb_buf <= pc - 32;
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else
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else
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pb <= pc;
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pb_buf <= pc;
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end if;
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end if;
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pb <= pb_buf;
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end if;
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end if;
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end process dpUCECHO;
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end process dpUCECHO;
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end RTL;
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end RTL;
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