URL
https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 5 |
| Line 9... |
Line 9... |
CLK : in std_logic
|
CLK : in std_logic
|
);
|
);
|
end ucecho;
|
end ucecho;
|
|
|
|
|
--signal declaration
|
|
architecture RTL of ucecho is
|
architecture RTL of ucecho is
|
|
|
|
--signal declaration
|
|
signal pb_buf : unsigned(7 downto 0);
|
|
|
begin
|
begin
|
dpUCECHO: process(CLK)
|
dpUCECHO: process(CLK)
|
begin
|
begin
|
if CLK' event and CLK = '1' then
|
if CLK' event and CLK = '1' then
|
if ( pc >= 97 ) and ( pc <= 122)
|
if ( pc >= 97 ) and ( pc <= 122)
|
then
|
then
|
pb <= pc - 32;
|
pb_buf <= pc - 32;
|
else
|
else
|
pb <= pc;
|
pb_buf <= pc;
|
end if;
|
end if;
|
|
pb <= pb_buf;
|
end if;
|
end if;
|
end process dpUCECHO;
|
end process dpUCECHO;
|
|
|
end RTL;
|
end RTL;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
