OpenCores
URL https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk

Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [include/] [ztex-descriptors.h] - Diff between revs 2 and 3

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 3
Line 46... Line 46...
   Reserved Product ID's:
   Reserved Product ID's:
 
 
   0.0.0.0              // default Product ID (no product specified)
   0.0.0.0              // default Product ID (no product specified)
   1.*.*.*              // may be used for experimental purposes
   1.*.*.*              // may be used for experimental purposes
   10.*.*.*             // used for ZTEX products
   10.*.*.*             // used for ZTEX products
 
   10.11.*.*            // ZTEX USB-FPGA-Module 1.2
 
   10.20.*.*            // ZTEX USB-Module 1.0
 
 
   Please contact me (http://www.ztex.de --> Impressum/Kontakt) if you want to register/reserve a Product ID (range).
   Please contact me (http://www.ztex.de --> Impressum/Kontakt) if you want to register/reserve a Product ID (range).
*/
*/
xdata at ZTEX_DESCRIPTOR_OFFS+6 BYTE PRODUCT_ID[4];
xdata at ZTEX_DESCRIPTOR_OFFS+6 BYTE PRODUCT_ID[4];
 
 
Line 61... Line 63...
 
 
/*
/*
    Standard interface capabilities:
    Standard interface capabilities:
        0.0  : EEPROM read/write, see ztex-eeprom.h
        0.0  : EEPROM read/write, see ztex-eeprom.h
        0.1  : FPGA configuration, see ztex-fpga.h
        0.1  : FPGA configuration, see ztex-fpga.h
 
        0.2  : Flash memeory suport, see ztex-flash1.h
*/
*/
xdata at ZTEX_DESCRIPTOR_OFFS+12 BYTE INTERFACE_CAPABILITIES[6];
xdata at ZTEX_DESCRIPTOR_OFFS+12 BYTE INTERFACE_CAPABILITIES[6];
 
 
/* Space for settings which depends on PRODUCT_ID, e.g extra capabilities */
/* Space for settings which depends on PRODUCT_ID, e.g extra capabilities */
xdata at ZTEX_DESCRIPTOR_OFFS+18 BYTE MODULE_RESERVED[12];
xdata at ZTEX_DESCRIPTOR_OFFS+18 BYTE MODULE_RESERVED[12];
Line 142... Line 145...
#endif
#endif
#ifdef[@CAPABILITY_FPGA;]
#ifdef[@CAPABILITY_FPGA;]
#nolf
#nolf
 + 2
 + 2
#endif
#endif
 
#ifdef[@CAPABILITY_FLASH;]
 
#nolf
 
 + 4
 
#endif
    .db 0
    .db 0
    .db 0
    .db 0
    .db 0
    .db 0
    .db 0
    .db 0
    .db 0
    .db 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.