| Line 21... |
Line 21... |
*/
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*/
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|
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#ifndef[ZTEX_ISR_H]
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#ifndef[ZTEX_ISR_H]
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#define[ZTEX_ISR_H]
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#define[ZTEX_ISR_H]
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|
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xdata BYTE prevSetupRequest = 0xff;
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xdata BYTE ep0_prev_setup_request = 0xff;
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xdata BYTE ep0_vendor_cmd_setup = 0;
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xdata WORD ISOFRAME_COUNTER[4] = {0, 0, 0, 0}; // counters for iso frames automatically reset by sync frame request
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xdata WORD ISOFRAME_COUNTER[4] = {0, 0, 0, 0}; // counters for iso frames automatically reset by sync frame request
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|
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/* *********************************************************************
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/* *********************************************************************
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***** toggleData ****************************************************
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***** toggleData ****************************************************
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| Line 84... |
Line 85... |
EP0BUF[1] = 3;
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EP0BUF[1] = 3;
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = i;
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EP0BCL = i;
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}
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}
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/* *********************************************************************
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***** ep0_payload_update ********************************************
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********************************************************************* */
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static void ep0_payload_update() {
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ep0_payload_transfer = ( ep0_payload_remaining > 64 ) ? 64 : ep0_payload_remaining;
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ep0_payload_remaining -= ep0_payload_transfer;
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}
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/* *********************************************************************
|
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***** ep0_vendor_cmd_su **********************************************
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********************************************************************* */
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static void ep0_vendor_cmd_su() {
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switch ( ep0_prev_setup_request ) {
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EP0_VENDOR_COMMANDS_SU;
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default:
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EP0CS |= 0x01; // set stall, unknown request
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** SUDAV_ISR *****************************************************
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***** SUDAV_ISR *****************************************************
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********************************************************************* */
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********************************************************************* */
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static void SUDAV_ISR () interrupt
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static void SUDAV_ISR () interrupt
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{
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{
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BYTE a;
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BYTE a;
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prevSetupRequest = bRequest;
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ep0_prev_setup_request = bRequest;
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SUDPTRCTL = 1;
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SUDPTRCTL = 1;
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// standard USB requests
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// standard USB requests
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switch ( bRequest ) {
|
switch ( bRequest ) {
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case 0x00: // get status
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case 0x00: // get status
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switch(SETUPDAT[0]) {
|
switch(SETUPDAT[0]) {
|
case 0x80: // self powered and remote
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case 0x80: // self powered and remote
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| Line 259... |
Line 280... |
}
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}
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// vendor request and commands
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// vendor request and commands
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switch ( bmRequestType ) {
|
switch ( bmRequestType ) {
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case 0xc0: // vendor request
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case 0xc0: // vendor request
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ep0_payload_remaining = (SETUPDAT[7] << 8) | SETUPDAT[6];
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ep0_payload_update();
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|
|
switch ( bRequest ) {
|
switch ( bRequest ) {
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case 0x22: // get ZTEX descriptor
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case 0x22: // get ZTEX descriptor
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SUDPTRCTL = 0;
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SUDPTRCTL = 0;
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = ZTEX_DESCRIPTOR_LEN;
|
EP0BCL = ZTEX_DESCRIPTOR_LEN;
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| Line 273... |
Line 297... |
default:
|
default:
|
EP0CS |= 0x01; // set stall, unknown request
|
EP0CS |= 0x01; // set stall, unknown request
|
}
|
}
|
break;
|
break;
|
case 0x40: // vendor command
|
case 0x40: // vendor command
|
switch ( bRequest ) {
|
/* vendor commands may overlap if they are send without pause. To avoid
|
EP0_VENDOR_COMMANDS_SU;
|
synchronization problems the setup sequences are executed in EP0OUT_ISR, i.e.
|
default:
|
after the first packet of payload date received. */
|
EP0CS |= 0x01; // set stall, unknown request
|
if ( SETUPDAT[7]!=0 || SETUPDAT[6]!=0 ) {
|
|
ep0_vendor_cmd_setup = 1;
|
|
EP0BCL = 0;
|
|
EXIF &= ~bmBIT4; // clear main USB interrupt flag
|
|
USBIRQ = bmBIT0; // clear SUADV IRQ
|
|
return; // don't clear HSNAK bit. This is done after the command has completed
|
}
|
}
|
|
ep0_vendor_cmd_su(); // setup sequences of vendor command with no payload ara executed immediately
|
|
EP0BCL = 0;
|
break;
|
break;
|
}
|
}
|
|
|
EP0CS |= 0x80;
|
EXIF &= ~bmBIT4; // clear main USB interrupt flag
|
EXIF &= ~bmBIT4;
|
USBIRQ = bmBIT0; // clear SUADV IRQ
|
USBIRQ = bmBIT0;
|
EP0CS |= 0x80; // clear the HSNAK bit
|
}
|
}
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** SOF_ISR *******************************************************
|
***** SOF_ISR *******************************************************
|
********************************************************************* */
|
********************************************************************* */
|
| Line 332... |
Line 363... |
EXIF &= ~bmBIT4;
|
EXIF &= ~bmBIT4;
|
USBIRQ = bmBIT5;
|
USBIRQ = bmBIT5;
|
}
|
}
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** AP0ACK_ISR ****************************************************
|
***** EP0ACK_ISR ****************************************************
|
********************************************************************* */
|
********************************************************************* */
|
void EP0ACK_ISR() interrupt
|
void EP0ACK_ISR() interrupt
|
{
|
{
|
EXIF &= ~bmBIT4;
|
EXIF &= ~bmBIT4; // clear USB interrupt flag
|
USBIRQ = bmBIT6;
|
USBIRQ = bmBIT6; // clear EP0ACK IRQ
|
}
|
}
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0IN_ISR *****************************************************
|
***** EP0IN_ISR *****************************************************
|
********************************************************************* */
|
********************************************************************* */
|
static void EP0IN_ISR () interrupt
|
static void EP0IN_ISR () interrupt
|
{
|
{
|
switch ( prevSetupRequest ) {
|
EUSB = 0; // block all USB interrupts
|
|
ep0_payload_update();
|
|
switch ( ep0_prev_setup_request ) {
|
EP0_VENDOR_REQUESTS_DAT;
|
EP0_VENDOR_REQUESTS_DAT;
|
default:
|
default:
|
EP0BCH = 0;
|
EP0BCH = 0;
|
EP0BCL = 0;
|
EP0BCL = 0;
|
}
|
}
|
EP0CS |= 0x80;
|
EXIF &= ~bmBIT4; // clear USB interrupt flag
|
EXIF &= ~bmBIT4;
|
EPIRQ = bmBIT0; // clear EP0IN IRQ
|
EPIRQ = bmBIT0;
|
EUSB = 1;
|
}
|
}
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0OUT_ISR ****************************************************
|
***** EP0OUT_ISR ****************************************************
|
********************************************************************* */
|
********************************************************************* */
|
static void EP0OUT_ISR () interrupt
|
static void EP0OUT_ISR () interrupt
|
{
|
{
|
switch ( prevSetupRequest ) {
|
EUSB = 0; // block all USB interrupts
|
|
if ( ep0_vendor_cmd_setup ) {
|
|
ep0_vendor_cmd_setup = 0;
|
|
ep0_payload_remaining = (SETUPDAT[7] << 8) | SETUPDAT[6];
|
|
ep0_vendor_cmd_su();
|
|
}
|
|
|
|
ep0_payload_update();
|
|
|
|
switch ( ep0_prev_setup_request ) {
|
EP0_VENDOR_COMMANDS_DAT;
|
EP0_VENDOR_COMMANDS_DAT;
|
}
|
}
|
|
|
EP0BCL = 1;
|
EP0BCL = 0;
|
|
|
EXIF &= ~bmBIT4;
|
EXIF &= ~bmBIT4; // clear main USB interrupt flag
|
EPIRQ = bmBIT1;
|
EPIRQ = bmBIT1; // clear EP0OUT IRQ
|
|
if ( ep0_payload_remaining == 0 ) {
|
|
EP0CS |= 0x80; // clear the HSNAK bit
|
|
}
|
|
EUSB = 1;
|
}
|
}
|
|
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP1IN_ISR *****************************************************
|
***** EP1IN_ISR *****************************************************
|
