URL https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk

Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [include/] [ztex-isr.h] - Diff between revs 4 and 5

Rev 4	Rev 5
Line 125...	Line 125...
`EP0BUF[1] = 0;`	`EP0BUF[1] = 0;`
`EP0BCH = 0;`	`EP0BCH = 0;`
`EP0BCL = 2;`	`EP0BCL = 2;`
`break;`	`break;`
`case 0x81: // interface (reserved)`	`case 0x81: // interface (reserved)`
`EP0BUF[0] = 0; // Always return zeros`	`EP0BUF[0] = 0; // always return zeros`
`EP0BUF[1] = 0;`	`EP0BUF[1] = 0;`
`EP0BCH = 0;`	`EP0BCH = 0;`
`EP0BCL = 2;`	`EP0BCL = 2;`
`break;`	`break;`
`case 0x82:`	`case 0x82:`
Line 299...	Line 299...
`}`	`}`
`break;`	`break;`
`case 0x40: // vendor command`	`case 0x40: // vendor command`
`/* vendor commands may overlap if they are send without pause. To avoid`	`/* vendor commands may overlap if they are send without pause. To avoid`
`synchronization problems the setup sequences are executed in EP0OUT_ISR, i.e.`	`synchronization problems the setup sequences are executed in EP0OUT_ISR, i.e.`
`after the first packet of payload date received. */`	`after the first packet of payload data received. */`
`if ( SETUPDAT[7]!=0 \|\| SETUPDAT[6]!=0 ) {`	`if ( SETUPDAT[7]!=0 \|\| SETUPDAT[6]!=0 ) {`
`ep0_vendor_cmd_setup = 1;`	`ep0_vendor_cmd_setup = 1;`
`EP0BCL = 0;`	`EP0BCL = 0;`
`EXIF &= ~bmBIT4; // clear main USB interrupt flag`	`EXIF &= ~bmBIT4; // clear main USB interrupt flag`
`USBIRQ = bmBIT0; // clear SUADV IRQ`	`USBIRQ = bmBIT0; // clear SUADV IRQ`