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[/] [usb_phy/] [trunk/] [rtl/] [verilog/] [usb_phy.v] - Diff between revs 4 and 7

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Rev 4 Rev 7
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////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
//  CVS Log
//
//
//  $Id: usb_phy.v,v 1.2 2002-09-16 16:06:37 rudi Exp $
//  $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $
//
//
//  $Date: 2002-09-16 16:06:37 $
//  $Date: 2003-10-19 17:40:13 $
//  $Revision: 1.2 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Author: rudi $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.2  2002/09/16 16:06:37  rudi
 
//               Changed top level name to be consistent ...
 
//
//               Revision 1.1.1.1  2002/09/16 14:26:59  rudi
//               Revision 1.1.1.1  2002/09/16 14:26:59  rudi
//               Created Directory Structure
//               Created Directory Structure
//
//
//
//
//
//
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///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
//
//
// Local Wires and Registers
// Local Wires and Registers
//
//
 
 
reg     [5:0]    rst_cnt;
reg     [4:0]    rst_cnt;
reg             usb_rst;
reg             usb_rst;
wire            reset;
wire            reset;
 
 
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
//
//
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//
//
// Generate an USB Reset is we see SE0 for at least 2.5uS
// Generate an USB Reset is we see SE0 for at least 2.5uS
//
//
 
 
always @(posedge clk)
always @(posedge clk)
        if(!rst)                        rst_cnt <= #1 5'h0;
        if(!rst)                        rst_cnt <= 5'h0;
        else
        else
        if(LineState_o != 2'h0)         rst_cnt <= #1 5'h0;
        if(LineState_o != 2'h0)         rst_cnt <= 5'h0;
        else
        else
        if(!usb_rst & fs_ce)            rst_cnt <= #1 rst_cnt + 5'h1;
        if(!usb_rst && fs_ce)           rst_cnt <= rst_cnt + 5'h1;
 
 
always @(posedge clk)
always @(posedge clk)
        usb_rst <= #1 (rst_cnt == 5'd31);
        usb_rst <= (rst_cnt == 5'h1f);
 
 
endmodule
endmodule
 
 
 
 
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