OpenCores

Rev 7	Rev 9
Line 36...	Line 36...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $`	`// $Id: usb_phy.v,v 1.4 2003-10-21 05:58:40 rudi Exp $`
`//`	`//`
`// $Date: 2003-10-19 17:40:13 $`	`// $Date: 2003-10-21 05:58:40 $`
`// $Revision: 1.3 $`	`// $Revision: 1.4 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2003/10/19 17:40:13 rudi`
	`// - Made core more robust against line noise`
	`// - Added Error Checking and Reporting`
	`// (See README.txt for more info)`
	`//`
`// Revision 1.2 2002/09/16 16:06:37 rudi`	`// Revision 1.2 2002/09/16 16:06:37 rudi`
`// Changed top level name to be consistent ...`	`// Changed top level name to be consistent ...`
`//`	`//`
`// Revision 1.1.1.1 2002/09/16 14:26:59 rudi`	`// Revision 1.1.1.1 2002/09/16 14:26:59 rudi`
`// Created Directory Structure`	`// Created Directory Structure`
Line 95...	Line 100...
`// Local Wires and Registers`	`// Local Wires and Registers`
`//`	`//`

`reg [4:0] rst_cnt;`	`reg [4:0] rst_cnt;`
`reg usb_rst;`	`reg usb_rst;`
`wire reset;`	`wire fs_ce;`
	`wire rst;`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Misc Logic`	`// Misc Logic`
`//`	`//`

`assign reset = rst & ~usb_rst;`

`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// TX Phy`	`// TX Phy`
`//`	`//`

`usb_tx_phy i_tx_phy(`	`usb_tx_phy i_tx_phy(`
`.clk( clk ),`	`.clk( clk ),`
`.rst( reset ),`	`.rst( rst ),`
`.fs_ce( fs_ce ),`	`.fs_ce( fs_ce ),`
`.phy_mode( phy_tx_mode ),`	`.phy_mode( phy_tx_mode ),`

`// Transciever Interface`	`// Transciever Interface`
`.txdp( txdp ),`	`.txdp( txdp ),`
Line 133...	Line 137...
`// RX Phy and DPLL`	`// RX Phy and DPLL`
`//`	`//`

`usb_rx_phy i_rx_phy(`	`usb_rx_phy i_rx_phy(`
`.clk( clk ),`	`.clk( clk ),`
`.rst( reset ),`	`.rst( rst ),`
`.fs_ce( fs_ce ),`	`.fs_ce( fs_ce ),`

`// Transciever Interface`	`// Transciever Interface`
`.rxd( rxd ),`	`.rxd( rxd ),`
`.rxdp( rxdp ),`	`.rxdp( rxdp ),`
Line 155...	Line 159...
`///////////////////////////////////////////////////////////////////`	`///////////////////////////////////////////////////////////////////`
`//`	`//`
`// Generate an USB Reset is we see SE0 for at least 2.5uS`	`// Generate an USB Reset is we see SE0 for at least 2.5uS`
`//`	`//`

	`ifdef USB_ASYNC_REST
	`always @(posedge clk or negedge rst)`
	`else
`always @(posedge clk)`	`always @(posedge clk)`
	`endif
`if(!rst) rst_cnt <= 5'h0;`	`if(!rst) rst_cnt <= 5'h0;`
`else`	`else`
`if(LineState_o != 2'h0) rst_cnt <= 5'h0;`	`if(LineState_o != 2'h0) rst_cnt <= 5'h0;`
`else`	`else`
`if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1;`	`if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1;`

Line 36...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $

//  $Id: usb_phy.v,v 1.4 2003-10-21 05:58:40 rudi Exp $

//

//

//  $Date: 2003-10-19 17:40:13 $

//  $Date: 2003-10-21 05:58:40 $

//  $Revision: 1.3 $

//  $Revision: 1.4 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.3  2003/10/19 17:40:13  rudi

//               - Made core more robust against line noise

//               - Added Error Checking and Reporting

//               (See README.txt for more info)

//

//               Revision 1.2  2002/09/16 16:06:37  rudi

//               Revision 1.2  2002/09/16 16:06:37  rudi

//               Changed top level name to be consistent ...

//               Changed top level name to be consistent ...

//

//

//               Revision 1.1.1.1  2002/09/16 14:26:59  rudi

//               Revision 1.1.1.1  2002/09/16 14:26:59  rudi

//               Created Directory Structure

//               Created Directory Structure

Line 95...

Line 100...

// Local Wires and Registers

// Local Wires and Registers

//

//

reg     [4:0]    rst_cnt;

reg     [4:0]    rst_cnt;

reg             usb_rst;

reg             usb_rst;

wire            reset;

wire            fs_ce;

wire            rst;

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Misc Logic

// Misc Logic

//

//

assign reset = rst & ~usb_rst;

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// TX Phy

// TX Phy

//

//

usb_tx_phy i_tx_phy(

usb_tx_phy i_tx_phy(

        .clk(           clk             ),

        .clk(           clk             ),

        .rst(           reset           ),

        .rst(           rst             ),

        .fs_ce(         fs_ce           ),

        .fs_ce(         fs_ce           ),

        .phy_mode(      phy_tx_mode     ),

        .phy_mode(      phy_tx_mode     ),

        // Transciever Interface

        // Transciever Interface

        .txdp(          txdp            ),

        .txdp(          txdp            ),

Line 133...

Line 137...

// RX Phy and DPLL

// RX Phy and DPLL

//

//

usb_rx_phy i_rx_phy(

usb_rx_phy i_rx_phy(

        .clk(           clk             ),

        .clk(           clk             ),

        .rst(           reset           ),

        .rst(           rst             ),

        .fs_ce(         fs_ce           ),

        .fs_ce(         fs_ce           ),

        // Transciever Interface

        // Transciever Interface

        .rxd(           rxd             ),

        .rxd(           rxd             ),

        .rxdp(          rxdp            ),

        .rxdp(          rxdp            ),

Line 155...

Line 159...

///////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////

//

//

// Generate an USB Reset is we see SE0 for at least 2.5uS

// Generate an USB Reset is we see SE0 for at least 2.5uS

//

//

`ifdef USB_ASYNC_REST

always @(posedge clk or negedge rst)

`else

always @(posedge clk)

always @(posedge clk)

`endif

        if(!rst)                        rst_cnt <= 5'h0;

        if(!rst)                        rst_cnt <= 5'h0;

        else

        else

        if(LineState_o != 2'h0)         rst_cnt <= 5'h0;

        if(LineState_o != 2'h0)         rst_cnt <= 5'h0;

        else

        else

        if(!usb_rst && fs_ce)           rst_cnt <= rst_cnt + 5'h1;

        if(!usb_rst && fs_ce)           rst_cnt <= rst_cnt + 5'h1;

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[/] [usb_phy/] [trunk/] [rtl/] [verilog/] [usb_phy.v] - Diff between revs 7 and 9