| Line 69... |
Line 69... |
reg SOFSent, next_SOFSent;
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reg SOFSent, next_SOFSent;
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wire SOFSyncEn;
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wire SOFSyncEn;
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wire [15:0]SOFTimer;
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wire [15:0]SOFTimer;
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reg SOFTimerClr, next_SOFTimerClr;
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reg SOFTimerClr, next_SOFTimerClr;
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// diagram signals declarations
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reg [7:0]i, next_i;
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// BINARY ENCODED state machine: SOFTx
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// BINARY ENCODED state machine: SOFTx
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// State codes definitions:
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// State codes definitions:
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`define START_STX 3'b000
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`define START_STX 3'b000
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`define WAIT_SOF_NEAR 3'b001
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`define WAIT_SOF_NEAR 3'b001
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`define WAIT_SP_GNT 3'b010
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`define WAIT_SP_GNT 3'b010
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`define WAIT_SOF_NOW 3'b011
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`define WAIT_SOF_NOW 3'b011
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`define SOF_FIN 3'b100
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`define SOF_FIN 3'b100
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`define DLY_SOF_CHK1 3'b101
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`define DLY_SOF_CHK2 3'b110
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reg [2:0]CurrState_SOFTx, NextState_SOFTx;
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reg [2:0]CurrState_SOFTx, NextState_SOFTx;
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// Machine: SOFTx
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// Machine: SOFTx
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
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always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
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begin
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begin
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NextState_SOFTx <= CurrState_SOFTx;
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NextState_SOFTx <= CurrState_SOFTx;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_SOFSent <= SOFSent;
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next_SOFSent <= SOFSent;
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next_SOFTimerClr <= SOFTimerClr;
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next_SOFTimerClr <= SOFTimerClr;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketWEn <= sendPacketWEn;
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next_i <= i;
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case (CurrState_SOFTx) // synopsys parallel_case full_case
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case (CurrState_SOFTx) // synopsys parallel_case full_case
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`START_STX:
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`START_STX:
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begin
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begin
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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end
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end
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| Line 133... |
Line 139... |
`SOF_FIN:
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`SOF_FIN:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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next_SOFTimerClr <= 1'b0;
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next_SOFTimerClr <= 1'b0;
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next_SOFSent <= 1'b0;
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next_SOFSent <= 1'b0;
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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if (sendPacketRdy == 1'b1)
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begin
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NextState_SOFTx <= `DLY_SOF_CHK1;
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next_i <= 8'h00;
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end
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end
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`DLY_SOF_CHK1:
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begin
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next_i <= i + 1'b1;
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if (i==8'hff)
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begin
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NextState_SOFTx <= `DLY_SOF_CHK2;
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next_sendPacketArbiterReq <= 1'b0;
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next_sendPacketArbiterReq <= 1'b0;
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next_i <= 8'h00;
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end
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end
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`DLY_SOF_CHK2:
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begin
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next_i <= i + 1'b1;
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if (i==8'hff)
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begin
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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end
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end
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end
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endcase
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endcase
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end
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end
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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| Line 157... |
Line 184... |
begin
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begin
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SOFSent <= 1'b0;
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SOFSent <= 1'b0;
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SOFTimerClr <= 1'b0;
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SOFTimerClr <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketWEn <= 1'b0;
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i <= 8'h00;
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end
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end
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else
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else
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begin
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begin
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SOFSent <= next_SOFSent;
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SOFSent <= next_SOFSent;
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SOFTimerClr <= next_SOFTimerClr;
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SOFTimerClr <= next_SOFTimerClr;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketWEn <= next_sendPacketWEn;
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i <= next_i;
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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