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[/] [usbhostslave/] [tags/] [rel_01_00/] [RTL/] [hostSlaveMux/] [hostSlaveMux.v] - Diff between revs 9 and 18

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////                                                              ////
 
////                                                              ////
 
//// This file is part of the usbhostslave opencores effort.
 
//// This file is part of the usbhostslave opencores effort.
 
//// <http://www.opencores.org/cores//>                           ////
 
//// <http://www.opencores.org/cores//>                           ////
 
////                                                              ////
 
////                                                              ////
 
//// Module Description:                                          ////
 
//// Module Description:                                          ////
 
//// 
//// Controls the select line for the mux that enables the sharing
 
 
 
//// of a single SerialInterfaceEgine between the hostController
 
 
 
//// and slaveController
 
 
 
//// Also a dumping area for any features common to host and slave 
 
 
//// operation. That is reset control and version number report.
 
////                                                              ////
 
////                                                              ////
 
//// To Do:                                                       ////
 
//// To Do:                                                       ////
 
//// 
//// 
////                                                              ////
 
////                                                              ////
 
//// Author(s):                                                   ////
 
//// Author(s):                                                   ////
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  dataIn,
 
  dataIn,
 
  dataOut,
 
  dataOut,
 
  address,
 
  address,
 
  writeEn,
 
  writeEn,
 
  strobe_i,
 
  strobe_i,
 
  clk,
 
  busClk,
 
  rst,
 
  usbClk,
 
  hostSlaveMuxSel  );
 
  hostSlaveMuxSel,
 
 
 
  rstFromWire,
 
 
 
  rstSyncToBusClkOut,
 
 
 
  rstSyncToUsbClkOut
 
 
 
);
 
 
 
 
 
 
 
 
 
output [7:0] SIEPortCtrlInToSIE;
 
output [7:0] SIEPortCtrlInToSIE;
 
input [7:0] SIEPortCtrlInFromHost;
 
input [7:0] SIEPortCtrlInFromHost;
 
input [7:0] SIEPortCtrlInFromSlave;
 
input [7:0] SIEPortCtrlInFromSlave;
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//hostSlaveMuxBI
 
//hostSlaveMuxBI
 
input [7:0] dataIn;
 
input [7:0] dataIn;
 
input address;
 
input address;
 
input writeEn;
 
input writeEn;
 
input strobe_i;
 
input strobe_i;
 
input clk;
 
input busClk;
 
input rst;
 
input usbClk;
 
 
 
input rstFromWire;
 
 
 
output rstSyncToBusClkOut;
 
 
 
output rstSyncToUsbClkOut;
 
output [7:0] dataOut;
 
output [7:0] dataOut;
 
input hostSlaveMuxSel;
 
input hostSlaveMuxSel;
 
 
 
 
 
reg [7:0] SIEPortCtrlInToSIE;
 
reg [7:0] SIEPortCtrlInToSIE;
 
wire [7:0] SIEPortCtrlInFromHost;
 
wire [7:0] SIEPortCtrlInFromHost;
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//hostSlaveMuxBI
 
//hostSlaveMuxBI
 
wire [7:0] dataIn;
 
wire [7:0] dataIn;
 
wire address;
 
wire address;
 
wire writeEn;
 
wire writeEn;
 
wire strobe_i;
 
wire strobe_i;
 
wire clk;
 
wire busClk;
 
wire rst;
 
wire usbClk;
 
 
 
wire rstSyncToBusClkOut;
 
 
 
wire rstSyncToUsbClkOut;
 
 
 
wire rstFromWire;
 
wire [7:0] dataOut;
 
wire [7:0] dataOut;
 
wire hostSlaveMuxSel;
 
wire hostSlaveMuxSel;
 
 
 
 
 
//internal wires and regs
 
//internal wires and regs
 
wire hostMode;
 
wire hostMode;
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  .dataIn(dataIn),
 
  .dataIn(dataIn),
 
  .dataOut(dataOut),
 
  .dataOut(dataOut),
 
  .address(address),
 
  .address(address),
 
  .writeEn(writeEn),
 
  .writeEn(writeEn),
 
  .strobe_i(strobe_i),
 
  .strobe_i(strobe_i),
 
  .clk(clk),
 
  .busClk(busClk),
 
  .rst(rst),
 
  .usbClk(usbClk),
 
  .hostMode(hostMode),
 
  .hostMode(hostMode),
 
  .hostSlaveMuxSel(hostSlaveMuxSel)  );
 
  .hostSlaveMuxSel(hostSlaveMuxSel),
 
 
 
  .rstFromWire(rstFromWire),
 
 
 
  .rstSyncToBusClkOut(rstSyncToBusClkOut),
 
 
 
  .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
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