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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Diff between revs 5 and 7

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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// $Id: processRxBit.v,v 1.2 2004-12-18 14:36:15 sfielding Exp $
// $Id: processRxBit.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
//
//
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      next_processRxBitRdy <= 1'b1;
      next_processRxBitRdy <= 1'b1;
      NextState_prRxBit <= `WAIT_BITS;
      NextState_prRxBit <= `WAIT_BITS;
    end
    end
    `WAIT_BITS:
    `WAIT_BITS:
    begin
    begin
      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
      begin
      begin
        NextState_prRxBit <= `DATA_RX_CHK_SE0;
        NextState_prRxBit <= `RES_RX_CHK;
        next_RxBits <= RxBitsIn;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
        next_processRxBitRdy <= 1'b0;
      end
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
      begin
      begin
        NextState_prRxBit <= `RES_RX_CHK;
        NextState_prRxBit <= `DATA_RX_CHK_SE0;
        next_RxBits <= RxBitsIn;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
        next_processRxBitRdy <= 1'b0;
      end
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
      begin
      begin
        NextState_prRxBit <= `RES_END_CHK1;
        NextState_prRxBit <= `IDLE_CHK_KBIT;
        next_RxBits <= RxBitsIn;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
        next_processRxBitRdy <= 1'b0;
      end
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
      begin
      begin
        NextState_prRxBit <= `IDLE_CHK_KBIT;
        NextState_prRxBit <= `RES_END_CHK1;
        next_RxBits <= RxBitsIn;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
        next_processRxBitRdy <= 1'b0;
      end
      end
    end
    end
    `IDLE_FIRST_BIT:
    `IDLE_FIRST_BIT:

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