| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// processTxByte
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processTxByte.v
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// $Id: processTxByte.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
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// Generated : 08/29/04 21:36:09
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// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processTxByte.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
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module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
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input clk;
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input [1:0] JBit;
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input [1:0] JBit;
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input [1:0] KBit;
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input [1:0] KBit;
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input processTxByteWEn;
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input rst;
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input [7:0] TxByteCtrlIn;
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input [7:0] TxByteCtrlIn;
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input [7:0] TxByteIn;
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input [7:0] TxByteIn;
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input USBWireGnt;
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input USBWireGnt;
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input USBWireRdy;
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input USBWireRdy;
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input clk;
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output processTxByteRdy;
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input processTxByteWEn;
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input rst;
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output USBWireCtrl;
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output USBWireCtrl;
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output [1:0] USBWireData;
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output [1:0] USBWireData;
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output USBWireReq;
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output USBWireReq;
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output USBWireWEn;
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output USBWireWEn;
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output processTxByteRdy;
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wire clk;
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wire [1:0] JBit;
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wire [1:0] JBit;
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wire [1:0] KBit;
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wire [1:0] KBit;
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reg processTxByteRdy, next_processTxByteRdy;
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wire processTxByteWEn;
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wire rst;
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wire [7:0] TxByteCtrlIn;
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wire [7:0] TxByteCtrlIn;
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wire [7:0] TxByteIn;
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wire [7:0] TxByteIn;
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reg USBWireCtrl, next_USBWireCtrl;
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reg USBWireCtrl, next_USBWireCtrl;
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reg [1:0] USBWireData, next_USBWireData;
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reg [1:0] USBWireData, next_USBWireData;
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wire USBWireGnt;
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wire USBWireGnt;
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wire USBWireRdy;
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wire USBWireRdy;
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reg USBWireReq, next_USBWireReq;
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reg USBWireReq, next_USBWireReq;
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reg USBWireWEn, next_USBWireWEn;
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reg USBWireWEn, next_USBWireWEn;
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wire clk;
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reg processTxByteRdy, next_processTxByteRdy;
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wire processTxByteWEn;
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wire rst;
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// diagram signals declarations
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// diagram signals declarations
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reg [3:0]i, next_i;
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reg [7:0]TxByte, next_TxByte;
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reg [7:0]TxByteCtrl, next_TxByteCtrl;
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reg [1:0]TXLineState, next_TXLineState;
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reg [1:0]TXLineState, next_TXLineState;
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reg [3:0]TXOneCount, next_TXOneCount;
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reg [3:0]TXOneCount, next_TXOneCount;
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reg [7:0]TxByteCtrl, next_TxByteCtrl;
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reg [7:0]TxByte, next_TxByte;
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reg [3:0]i, next_i;
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// BINARY ENCODED state machine: prcTxB
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// BINARY ENCODED state machine: prcTxB
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// State codes definitions:
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// State codes definitions:
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`define START_PTBY 4'b0000
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`define START_PTBY 4'b0000
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`define PTBY_WAIT_EN 4'b0001
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`define PTBY_WAIT_EN 4'b0001
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| Line 76... |
Line 106... |
`define STOP_CHK 4'b1011
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`define STOP_CHK 4'b1011
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`define STOP_SND_J 4'b1100
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`define STOP_SND_J 4'b1100
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`define STOP_SND_IDLE 4'b1101
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`define STOP_SND_IDLE 4'b1101
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`define STOP_FIN 4'b1110
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`define STOP_FIN 4'b1110
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reg [3:0] CurrState_prcTxB;
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reg [3:0]CurrState_prcTxB, NextState_prcTxB;
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reg [3:0] NextState_prcTxB;
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//--------------------------------------------------------------------
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// Machine: prcTxB
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// Machine: prcTxB
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//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
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always @ (TxByteIn or TxByteCtrlIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
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begin
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begin : prcTxB_NextState
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NextState_prcTxB <= CurrState_prcTxB;
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NextState_prcTxB <= CurrState_prcTxB;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_processTxByteRdy <= processTxByteRdy;
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next_processTxByteRdy <= processTxByteRdy;
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next_USBWireData <= USBWireData;
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next_USBWireData <= USBWireData;
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next_USBWireCtrl <= USBWireCtrl;
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next_USBWireCtrl <= USBWireCtrl;
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| Line 138... |
Line 164... |
next_TxByteCtrl <= TxByteCtrlIn;
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next_TxByteCtrl <= TxByteCtrlIn;
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next_i <= 4'h0;
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next_i <= 4'h0;
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end
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end
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end
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end
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`PTBY_WAIT_GNT:
|
`PTBY_WAIT_GNT:
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begin
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if (USBWireGnt == 1'b1)
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if (USBWireGnt == 1'b1)
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begin
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begin
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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next_i <= 4'h0;
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next_i <= 4'h0;
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end
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end
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end
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`SEND_BYTE_UPDATE_BYTE:
|
`SEND_BYTE_UPDATE_BYTE:
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begin
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begin
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next_i <= i + 1'b1;
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next_i <= i + 1'b1;
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next_TxByte <= {1'b0, TxByte[7:1] };
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next_TxByte <= {1'b0, TxByte[7:1] };
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if (TxByte[0] == 1'b1) //If this bit is 1, then
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if (TxByte[0] == 1'b1) //If this bit is 1, then
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| Line 154... |
Line 182... |
//increment 'TXOneCount'
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//increment 'TXOneCount'
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else //else this is a zero bit
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else //else this is a zero bit
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begin
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begin
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next_TXOneCount <= 4'h1;
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next_TXOneCount <= 4'h1;
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//reset 'TXOneCount'
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//reset 'TXOneCount'
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if (TXLineState == JBit) next_TXLineState <= KBit;
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if (TXLineState == JBit)
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next_TXLineState <= KBit;
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//toggle the line state
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//toggle the line state
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else next_TXLineState <= JBit;
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else
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next_TXLineState <= JBit;
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end
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end
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
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end
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end
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`SEND_BYTE_WAIT_RDY:
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`SEND_BYTE_WAIT_RDY:
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begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_prcTxB <= `SEND_BYTE_CHK;
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NextState_prcTxB <= `SEND_BYTE_CHK;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= TXLineState;
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next_USBWireData <= TXLineState;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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end
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end
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end
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`SEND_BYTE_CHK:
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`SEND_BYTE_CHK:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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if (TXOneCount == 4'h6)
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if (TXOneCount == 4'h6)
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begin
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NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
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NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
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end
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else if (i != 4'h8)
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else if (i != 4'h8)
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begin
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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end
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else
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else
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begin
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NextState_prcTxB <= `STOP_CHK;
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NextState_prcTxB <= `STOP_CHK;
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end
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end
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end
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`SEND_BYTE_BIT_STUFF:
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`SEND_BYTE_BIT_STUFF:
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begin
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begin
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next_TXOneCount <= 4'h1;
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next_TXOneCount <= 4'h1;
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//reset 'TXOneCount'
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//reset 'TXOneCount'
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if (TXLineState == JBit) next_TXLineState <= KBit;
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if (TXLineState == JBit)
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next_TXLineState <= KBit;
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//toggle the line state
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//toggle the line state
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else next_TXLineState <= JBit;
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else
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next_TXLineState <= JBit;
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
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end
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end
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`SEND_BYTE_WAIT_RDY2:
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`SEND_BYTE_WAIT_RDY2:
|
|
begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
|
begin
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begin
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NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
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NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= TXLineState;
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next_USBWireData <= TXLineState;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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end
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end
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end
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`SEND_BYTE_CHK_FIN:
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`SEND_BYTE_CHK_FIN:
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begin
|
begin
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next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
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if (i == 4'h8)
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if (i == 4'h8)
|
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begin
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NextState_prcTxB <= `STOP_CHK;
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NextState_prcTxB <= `STOP_CHK;
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end
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else
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else
|
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begin
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
|
end
|
end
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end
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`STOP_SND_SE0_2:
|
`STOP_SND_SE0_2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
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| Line 215... |
Line 261... |
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
end
|
end
|
end
|
end
|
`STOP_SND_SE0_1:
|
`STOP_SND_SE0_1:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `STOP_SND_SE0_2;
|
NextState_prcTxB <= `STOP_SND_SE0_2;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
end
|
end
|
|
end
|
`STOP_CHK:
|
`STOP_CHK:
|
|
begin
|
if (TxByteCtrl == `DATA_STOP)
|
if (TxByteCtrl == `DATA_STOP)
|
|
begin
|
NextState_prcTxB <= `STOP_SND_SE0_1;
|
NextState_prcTxB <= `STOP_SND_SE0_1;
|
|
end
|
else
|
else
|
|
begin
|
NextState_prcTxB <= `PTBY_WAIT_EN;
|
NextState_prcTxB <= `PTBY_WAIT_EN;
|
|
end
|
|
end
|
`STOP_SND_J:
|
`STOP_SND_J:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
| Line 259... |
Line 313... |
NextState_prcTxB <= `PTBY_WAIT_EN;
|
NextState_prcTxB <= `PTBY_WAIT_EN;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : prcTxB_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_prcTxB <= `START_PTBY;
|
CurrState_prcTxB <= `START_PTBY;
|
else
|
else
|
CurrState_prcTxB <= NextState_prcTxB;
|
CurrState_prcTxB <= NextState_prcTxB;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : prcTxB_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
i <= 4'h0;
|
|
TxByte <= 8'h00;
|
|
TxByteCtrl <= 8'h00;
|
|
TXLineState <= 2'b0;
|
|
TXOneCount <= 4'h0;
|
|
processTxByteRdy <= 1'b0;
|
processTxByteRdy <= 1'b0;
|
USBWireData <= 2'b00;
|
USBWireData <= 2'b00;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireReq <= 1'b0;
|
USBWireReq <= 1'b0;
|
USBWireWEn <= 1'b0;
|
USBWireWEn <= 1'b0;
|
|
i <= 4'h0;
|
|
TxByte <= 8'h00;
|
|
TxByteCtrl <= 8'h00;
|
|
TXLineState <= 2'b0;
|
|
TXOneCount <= 4'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
i <= next_i;
|
|
TxByte <= next_TxByte;
|
|
TxByteCtrl <= next_TxByteCtrl;
|
|
TXLineState <= next_TXLineState;
|
|
TXOneCount <= next_TXOneCount;
|
|
processTxByteRdy <= next_processTxByteRdy;
|
processTxByteRdy <= next_processTxByteRdy;
|
USBWireData <= next_USBWireData;
|
USBWireData <= next_USBWireData;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireReq <= next_USBWireReq;
|
USBWireReq <= next_USBWireReq;
|
USBWireWEn <= next_USBWireWEn;
|
USBWireWEn <= next_USBWireWEn;
|
|
i <= next_i;
|
|
TxByte <= next_TxByte;
|
|
TxByteCtrl <= next_TxByteCtrl;
|
|
TXLineState <= next_TXLineState;
|
|
TXOneCount <= next_TXOneCount;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
